FOD2200SD 데이터 시트보기 (PDF) - Fairchild Semiconductor
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FOD2200SD Datasheet PDF : 11 Pages
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Package Dimensions
Through Hole
4
3
5
6
21
7
8
PIN 1
ID.
0.270 (6.86)
0.250 (6.35)
0.200 (5.08)
0.140 (3.55)
0.022 (0.56)
0.016 (0.41)
0.390 (9.91)
0.370 (9.40)
0.070 (1.78)
0.045 (1.14)
0.020 (0.51) MIN
0.154 (3.90)
0.120 (3.05)
0.100 (2.54) TYP
0.016 (0.40)
0.008 (0.20)
15° MAX
0.300 (7.62)
TYP
Surface Mount
0.390 (9.91)
0.370 (9.40)
4
3
2
1
PIN 1
ID.
0.270 (6.86)
0.250 (6.35)
5
6
7
8
0.070 (1.78)
0.045 (1.14)
0.300 (7.62)
TYP
0.020 (0.51)
MIN
0.016 (0.41)
0.008 (0.20)
0.022 (0.56)
0.016 (0.41)
0.100 (2.54)
TYP
Lead Coplanarity : 0.004 (0.10) MAX
0.045 (1.14)
0.315 (8.00)
MIN
0.405 (10.30)
MAX.
Note:
All dimensions are in inches (millimeters)
0.4" Lead Spacing
4
3
21
PIN 1
ID.
0.270 (6.86)
0.250 (6.35)
5
6
7
8
0.200 (5.08)
0.140 (3.55)
0.022 (0.56)
0.016 (0.41)
0.390 (9.91)
0.370 (9.40)
0.070 (1.78)
0.045 (1.14)
0.004 (0.10) MIN
0.154 (3.90)
0.120 (3.05)
0.100 (2.54) TYP
0.016 (0.40)
0.008 (0.20)
0° to 15°
0.400 (10.16)
TYP
8-Pin DIP – Land Pattern
0.070 (1.78)
0.060 (1.52)
0.295 (7.49)
0.415 (10.54)
0.100 (2.54)
0.030 (0.76)
©2004 Fairchild Semiconductor Corporation
FOD2200 Rev. 1.0.1
8
www.fairchildsemi.com
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