Operating modes
M48Z512A, M48Z512AY, M48Z512AV
Figure 6. WRITE enable controlled, WRITE AC waveforms
tAVAV
A0-A18
VALID
tAVEL
tAVWH
tWHAX
E
tAVWL
tWLWH
W
duct(s) DQ0-DQ7
tWLQZ
tWHDX
DATA INPUT
tDVWH
tWHQX
Pro 1. Output enable (G) = high.
lete Figure 7. Chip enable controlled, WRITE AC waveforms
bso A0-A18
t(s) - O E
roduc W
olete P DQ0-DQ7
tAVEL
tAVWL
tAVAV
VALID
tAVEH
tELEH
tEHAX
tEHDX
DATA INPUT
tDVEH
Obs 1. Output enable (G) = high.
AI01222
AI01223
10/21
Doc ID 5146 Rev 9