MB84VA2002 데이터 시트보기 (PDF) - Fujitsu

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MB84VA2002

8M (× 8/× 16) FLASH MEMORY & 2M (× 8) STATIC RAM

Fujitsu 

MB84VA2002-10/MB84VA2003-10

s AC CHARACTERISTICS

• CE Timing

Parameter

Symbols

JEDEC Standard

Description

—

tCCR CE Recover Time

• Timing Diagram for alternating SRAM to Flash

CEf

tCCR

CE1s

tCCR

CE2s

Test Setup

-10

Unit

—

Min.

0

ns

tCCR

tCCR

• Read Only Operations Characteristics (Flash)

Parameter

Symbols

JEDEC Standard

Description

tAVAV

tRC Read Cycle Time

tAVQV

tACC Address to Output Delay

tELQV

tCEf Chip Enable to Output Delay

tGLQV

tOE Output Enable to Output Delay

tEHQZ

tDF Chip Enable to Output High-Z

tGHQZ

tDF Output Enable to Output High-Z

tAXQX

tOH

Output Hold Time From Addresses,

CEf or OE, Whichever Occurs First

—

tREADY RESET Pin Low to Read Mode

—

tELFL

tELFH

CE or BYTE Switching Low or High

Note: Test Conditions–Output Load: 1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level

Input: 1.5 V

Output: 1.5 V

12

Test

Setup

—

CEf = VIL

OE = VIL

OE = VIL

—

—

—

—

—

—

-10

(Note)

Unit

Min. Max.

100

—

ns

—

100 ns

—

100 ns

—

40

ns

—

30

ns

—

30

ns

0

—

ns

—

20

µs

—

5

ns

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