µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
5.2 Clock Generator
The clock generator operates according to the statuses of the processor clock control register (PCC) and
the system clock control register (SCC). Two types of clock are provided: main system clock and subsystem
clock, and the instruction execution time can be changed.
• 0.95 µs / 1.91 µs / 15.3 µs (operated with main system clock at 4.19 MHz)
• 122 µs (operated with subsystem clock at 32.768 kHz)
Figure 5-1. Clock Generator Block Diagram
XT1
Subsystem
fXT
clock generator
XT2
X1
Main system fX
clock generator
X2
Watch timer
• Basic interval timer (BT)
• Timer/event counter
•
•
Serial interface
Watch timer
• A /D converter
(successive approximation type)
• INT0 noise eliminator
• Clock output circuit
1/2 1/16
1/2 to 1/4096
Frequency divider
WM.3
SCC
SCC3
SCC0
PCC
PCC0
PCC1
4
PCC2
HALT Note
PCC3
STOP Note
PCC2, PCC3
clear signal
Oscillator
disable
signal
STOP F/F
QS
R
Selec-
tor
Selec-
tor
Frequency
divider
1/4
Φ
• CPU
• INT0 noise
eliminator
• Clock output
circuit
HALT F/F
S
RQ
Wait release signal from BT
RESET signal
Standby release signal from
interrupt control circuit
Note Instruction execution
Remarks
1. fX = Main system clock frequency
2. fXT = Subsystem clock frequency
3. Φ = CPU clock
4. PCC: Processor clock control register
5. SCC: System clock control register
6. One clock cycle (tCY) at Φ is equal to one machine cycle of an instruction.
For tCY, refer to AC Characteristics in 10. ELECTRICAL SPECIFICATIONS.
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