AC Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
0.4V to 2.4V
5 ns
1.5V
See Figures 1 and 2
A62S6308 Series
TTL
TTL
CL
30pF
CL
5pF
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ1,
tCLZ2, tOHZ, tOLZ, tCHZ1,
tCHZ2, tWHZ, and tOW
Data Retention Characteristics (TA = 0°C to + 70°C or -25°C to 85°C)
Symbol
VDR1
Parameter
Min.
2.0
Max.
3.6
Unit
Conditions
V
CE1 ≥ VCC - 0.2V
VDR2
VCC for Data Retention
2.0
3.6
CE2 ≤ 0.2V
V
CE1 ≥ VCC - 0.2V or
CE1 ≤ 0.2V
ICCDR1
Data Retention Current
S-Version
SI-Version
-
10*
-
20**
ICCDR2
S-Version
SI-Version
-
10*
-
20**
tCDR
Chip Disable to Data Retention Time
0
-
tR
Operation Recovery Time
tRC
-
tVR
VCC Rise Time from Data Retention Voltage
to Operating Voltage
5
-
** A62S6308-70S/10S
* A62S6308-70SI/10SI
ICCDR: Max. 3µA at TA = 0°C + 40°C
ICCDR: Max. 3µA at TA = 0°C + 40°C
VCC = 2.0V
µA CE1 ≥ VCC - 0.2V
CE2 ≥ VCC - 0.2V
VIN ≥ 0V
VCC = 2.0V
µA
CE2 ≤ 0.2V
VIN ≥ 0V
ns
ns
See Retention Waveform
ms
(October, 1998, Version 2.0)
10
AMIC Technology, Inc.