XWM8721EDS(2000) 데이터 시트보기 (PDF) - Wolfson Microelectronics plc
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XWM8721EDS
(Rev.:2000)
(Rev.:2000)
Wolfson Microelectronics plc
XWM8721EDS Datasheet PDF : 34 Pages
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WM8721
DIGITAL AUDIO INTERFACE – MASTER MODE
Product Preview
BCLK
(Output)
DACLRC
(Output)
DACDAT
tDLT
tDL
tDHT
Figure 2 Digital Audio Data Timing - Master Mode
Test Conditions
AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
DACLRC propagation delay
tDL
from BCLK falling edge
DACDAT setup time to
tDST
BCLCK rising edge
DACDAT hold time from
tDHT
BCLK rising edge
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
10
ns
10
ns
10
ns
DIGITAL AUDIO INTERFACE – SLAVE MODE
tBCH
tBCL
BCLK
tBCY
DACLRC
DACDAT
tDS
tLRH
tLRSU
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, slave mode, fs = 48kHz, MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
BCLK cycle time
tBCY
BCLK pulse width high
tBCH
BCLK pulse width low
tBCL
DACLRC set-up time to
BCLK rising edge
tLRSU
DACLRC hold time from
tLRH
BCLK rising edge
DACDAT set-up time to
tDS
BCLK rising edge
DACDAT hold time from
tDH
BCLK rising edge
TEST CONDITIONS
MIN
TYP
MAX
UNIT
50
ns
20
ns
20
ns
10
ns
10
ns
10
ns
10
ns
WOLFSON MICROELECTRONICS LTD
PP Rev 1.3 November 2000
7
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