DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating
Rev. 2 — 3 September 2010
Product data sheet
1. General description
The DAC1005D650 is a high-speed 10-bit dual-channel Digital-to-Analog Converter
(DAC) with selectable 2×, 4× or 8× interpolating filters optimized for multi-carrier wireless
transmitters.
Thanks to its digital on-chip modulation, the DAC1005D650 allows the complex I and Q
inputs to be converted up from BaseBand (BB) to IF. The mixing frequency is adjusted
using a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator
(NCO). The phase is controlled by a 16-bit register.
Two modes of operation are available: separate data ports or a single interleaved
high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into
its original I and Q data and then latched.
The DAC1005D650 also includes a 2×, 4× and 8× clock multiplier which provides the
appropriate internal clocks and an internal regulator to adjust the output full-scale current.
2. Features and benefits
Dual 10-bit resolution
650 Msps maximum update rate
Selectable 2×, 4× or 8× interpolation
IMD3: 79 dBc; fs = 640 Msps; fo = 96 MHz
SFDR: 75 dBc; fdata = 80 MHz;
fs = 640 Msps; fo = 19 MHz; PLL on
Typical 0.95 W power dissipation at 4×
filters
interpolation
Input data rate up to 160 Msps
Power-down and Sleep modes
Very low noise cap-free integrated PLL Differential scalable output current from
1.6 mA to 20 mA
32-bit programmable NCO frequency On-chip 1.25 V reference
Dual-port or Interleaved data modes External analog offset control
(10-bit auxiliary DACs)
1.8 V and 3.3 V power supplies
Internal digital offset control
LVDS compatible clock
Inverse (sin x) / x function
Two’s complement or binary offset Fully compatible SPI port
data format
3.3 V CMOS input buffers
Industrial temperature range from
−40 °C to +85 °C