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FM24CL64B(2014) 데이터 시트보기 (PDF) - Cypress Semiconductor
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FM24CL64B
(Rev.:2014)
64-Kbit (8K × 8) Serial (I2C) F-RAM
Cypress Semiconductor
FM24CL64B Datasheet PDF : 19 Pages
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FM24CL64B
Power Cycle Timing
Over the
Operating Range
Parameter
Description
Min
t
PU
Power-up V
DD
(min) to first access (START condition)
1
t
PD
Last access (STOP condition) to power-down (V
DD
(min))
0
t
VR
[8, 9]
V
DD
power-up ramp rate
30
t
VF
[8, 9]
V
DD
power-down ramp rate
30
Figure 16. Power Cycle Timing
VDD
VDD(min)
tVR
tPU
VDD(min)
tVF
tPD
SDA
I2C START
I2C STOP
Max Unit
–
ms
–
µs
–
µs/V
–
µs/V
Note
8. Slope measured at any point on the V
DD
waveform.
9. Guaranteed by design.
Document Number: 001-84458 Rev. *D
Page 13 of 19
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