LC75817NE, 75817NW
GENERAL
PORT
COMMON
DRIVER
VLCD
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VDD
VSS
TEST
CONTRAST
ADJUSTER
VDET
TIMING
GENERATOR
CLOCK
GENERATOR
INSTRUCTION
DECODER
SEGMENT DRIVER
ADRAM
60
bits
LATCH
CGRAM
5 × 9 × 16
bits
CGROM
5 × 9 × 240
bits
INSTRUCTION
REGISTER
ADDRESS
COUNTER
ADDRESS
REGISTER
DCRAM
48 × 8
bits
SHIFT REGISTER
CCB INTERFACE
KEY BUFFER
KEY SCAN
Blocks that are reset
3. Output pin states during the system reset
Output pin
S1 to S59
S60/COM10
COM1 to COM9
KS1 to KS6
P1 to P4
DO
State during reset
L (VLCD4)
L (VLCD4)*20
L (VLCD4)
L (VSS)
L (VSS)
H *21
Notes: *20. This output pin is forcibly set to the segment output function and held at the low level (VLCD4). However, when a “set display technique”
instruction is executed, the segment output or the common output function is selected as specified by that instruction.
*21. Since this output pin is an open-drain output, a pull-up resistor (between 1 kΩ and 10 kΩ) is required. This pin is held at the high level even if a
key data read operation is performed before executing a “set key scan output state” instruction.
No. 6144-30/43