TDA9160 데이터 시트보기 (PDF) - Philips Electronics

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TDA9160

PAL/NTSC/SECAM decoder/sync processor

Philips Electronics 

Philips Semiconductors

PAL/NTSC/SECAM decoder/sync processor

Preliminary specification

TDA9160

SYMBOL

PARAMETER

CONDITIONS

MIN.

SECOND LOOP

ϕ

control sensitivity

tCR

control range of the positive

going edge of horizontal drive

to flyback

td

delay between second loop

reference and mid-sync of

processed video

HS = 00; note 4

300

13.5

−

HORIZONTAL SHIFT

SR

horizontal shift range

HORIZONTAL DRIVE OUTPUT (PIN 18)

R18

output resistance

I18

output current

duty cycle of output current

63 steps

on-state

−2.2

−

−

−

HORIZONTAL FLYBACK INPUT (PIN 19)

VHB

switching level for horizontal

−

blanking

Vϕ2

switching level for phase two

−

loop

V19

maximum input voltage

−

ZI

input impedance

10

Soft start

CR

duty cycle control range

2

soft start time

200

Vertical section (note 3)

VERTICAL OSCILLATOR

ffr

free running frequency

divider ratio 628

−

fLR

frequency locking range

43

LR

divider locking range

488

VERTICAL SAWTOOTH (PIN 11)

V11(p-p)

voltage amplitude level

(peak-to-peak value)

VS = 1F; C = 100 nF; −

R = 39 kΩ

Idis

Icharge

discharge current

−

charge current set by external f = 50 Hz; VS = 1F −

resistor

CR

vertical slope control range 63 steps

−14

TYP.

−

−

3

−

−

−

55

0.3

3.8

−

−

−

300

50

−

625

3.5

1

19

−

MAX.

UNIT

−

µs/µs

−

µs

−

µs

+2.2

50

10

−

−

−

VCC

−

55

500

µs

Ω

mA

%

V

V

V

MΩ

%

lines

−

Hz

64

Hz

722

−

V

−

mA

−

µA

+14

%

December 1991

18

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