UCB1500 데이터 시트보기 (PDF) - Philips Electronics

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UCB1500

PCI to AC97 bridge/host controller

Philips Electronics 

Philips Semiconductors

UCB1500

PCI to AC97 bridge/host controller

9397 750 06854

Objective specification

[07-06]: Status Register

Table 16: Status Register bit description

Bit

Description

15

PERR detected

Set to ‘1’ whenever parity error is detected. Write ‘1’ to clear.

14

SERR asserted

Set to ‘1’ if UCB1500 asserted SERR. Write ‘1' to clear.

13

Received master abort

If set, UCB1500 has received master abort during its slave operation. Write ‘1’ to

clear.

12

Received target abort

If set, UCB1500 has received target abort during its master operation. Write `1'

to clear

11(r)

Target abort

Always ‘0’; UCB1500 never signals target abort.

10-9(r) Timing

Always 01b; wait state during slave access to UCB1500.

8

PERR reported

Not implemented, always 0.

7(r)

Fast back-to-back capable

Always ‘1’; NO wait state between PCI cycles.

6(r)

User Definable features

Always ‘0’; device does not support user definable features.

5(r)

66 MHz capable bit

Always ‘0’; device is 33 MHz device only.

4(r)

Capabilities bit (read only)

Always ‘1’; capabilities present.

3-0

Reserved.

[08]: Revision ID (read only): Current revision of chip = 1.

[0B-09]: Class Code Register (read only): Value = 040100h for multimedia device,

audio. Programmable through EEPROM interface or register 47-45h.

[0C]: Cache Line Size (read only): Always 0; no cache supported.

[0D]: Latency Timer

Table 17: Latency Timer register bit description

Bit

Description

7-4

Latency Timer

Bits 7-4 of the latency timer, in units of PCI clocks * 16.

3-0(r)

Latency Timer

Bits 3-0 of the latency timer. These bits are read only and are always 0000b,

giving timer granularity of 16 PCI clocks.

[0E]: Header Type (read only): Always 0.

Rev. 01 — 4 February 2000

© Philips Electronics N.V. 2000. All rights reserved.

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