SA9101 데이터 시트보기 (PDF) - South African Micro Electronic Systems
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SA9101 Datasheet PDF : 40 Pages
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SA9101
Signal Processing
General
PCM line bit rate
:
2048 kbps ±50 ppm
Single frame length :
256 bit, No. 1 ... 256
Framing frequency :
8 kHz
Organization
:
32 timeslots, No. 0 ... 31
with 8 bits each, No. 1 ... 8
Timeslot 0 is reserved for frame alignment word and service Information. Switching
between the two word framing formats (Doubleframe/CRC-Multiframe) is done via the
Control Register.
Line Interfacing
- Dual rail data with HDB3 coding in conjunction with double violation detection or
extended code violation detection. Errors are counted by the Code Violation
Counter. (Selectable between 8 and 10 bit counter.)
- Single rail unipolar data with no zero suppression algorithm.
General alarms
- AIS
: Detection and Transmission.
- NOS : No Signal Detection.
- RAI
: Remote Alarm Indication and Transmission.
Channel Assignment (including Timeslot 0)
The channel (timeslot) assignment from the PCM line to the system internal highway is
performed without any changes of channel numbering (TS0,...,TS31). In the receive
direction, the contents of timeslot 0 are switched through transparently. In the transmit
direction, the contents of timeslot 0 of the outgoing PCM frame are normally generated
by the SA9101. Additionally, one of three Transparent Modes can be selected to achieve
transparency either for Sn bit information, Sn and Si bit information or for all of the data
in timeslot 0.
S and S bits can be fed through from the system interface (DXI) by activating transparent
n
i
mode CR5B4, known as Timeslot 0 Signalling Transparent mode. Only Sn bits can be
fed through DXI when the Extended Signalling Transparent mode is activated.
Priority is in the following order:
Highest - Timeslot 0 Transparent Mode (CR5B5)
Medium - Timeslot 0 Extended Signalling Transparent Mode (CX1B6)
Lowest - Timeslot 0 Signalling Transparent Mode (CR5B4)
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