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LF2250QC20

12 x 10-bit Matrix Multiplier

LOGIC Devices 

DEVICES INCORPORATED

LF2250

12 x 10-bit Matrix Multiplier

TABLE 4. COEFF. REG. UPDATE

CWE1-0

00

01

10

11

COEFFICIENT SET

Hold All Registers

KA1, KB1, KC1

KA2, KB2, KC2

KA3, KB3, KC3

DETAILS OF OPERATION

3 x 3 Matrix Multiplier — Mode 00

In this mode, all three input ports (A,

B, C) and all three output ports (X, Y,

Z) are utilized to implement a 3 x 3

matrix multiplication (triple dot

product). Each rounded 12-bit output

is the sum of all three input words

multiplied by the appropriate coeffi-

cients (Table 5). The pipeline latency

for this mode is five clock cycles.

Therefore, the sum of products will

be output five clock cycles after the

input data has been latched. New

output data is subsequently available

every clock cycle thereafter.

9-Tap FIR Filter — Mode 01

This mode utilizes the 12-bit A and B

data input ports as well as the 16-bit

CASIN port. The input data should

be presented to the A and B ports

simultaneously. The resulting 9-

sample response, which is half-LSB

rounded to 16 bits, begins after five

clock cycles and ends after 13 clock

cycles (Table 5). The pipeline latency

from the input of an impulse response

to the center of the output response is

nine clock cycles. The latency from

the CASIN port to the CASOUT port

is four clock cycles. New output data

is available every clock cycle.

3 x 3-Pixel Convolver — Mode 10

When configured in this mode, line

delayed data is loaded through the A,

B, and C input ports. During each

cycle, a new rounded 16-bit output

(comprising of the summation of the

multiplications of the last nine data

inputs with their related coefficients)

becomes available (Table 5). The

CASIN term is also added to each

new output. The internal bus struc-

ture and pipeline delays allow new

input data to be added every cycle

while maintaining the structure of the

filtering operation. This addition of

new data every cycle produces the

effect of the convolution window

moving to the next pixel column.

4 x 2-Pixel Convolver — Mode 11

Using the A and B ports, input data is

loaded and multiplied by the on-

board coefficients. These products

are then summed with the CASIN

data and rounded to create the 16-bit

output. The cascade ports allow

multiple devices to be used together

for use with larger kernels. As with

Mode 10, each cycle results in a 16-bit

output created from the products and

summations performed.

TABLE 5. LATENCY EQUATIONS

3 x 3 Matrix Multiplier — Mode 00

X(n+4) = A(n)KA1(n) + B(n)KB1(n) + C(n)KC1(n)

Y(n+4) = A(n)KA2(n) + B(n)KB2(n) + C(n)KC2(n)

Z(n+4) = A(n)KA3(n) + B(n)KB3(n) + C(n)KC3(n)

9-Tap FIR Filter — Mode 01

CASOUT(n+12) = A(n+8)KA3(n+8) + A(n+7)KA2(n+7) + A(n+6)KA1(n+6)

+ B(n+5)KB3(n+8) + B(n+4)KB2(n+7) + B(n+3)KB1(n+6)

+ B(n+2)KC3(n+8) + B(n+1)KC2(n+7) + B(n)KC1(n+6)

+ CASIN(n+9)

CASOUT(n+6)

3 x 3-Pixel Convolver — Mode 10

= A(n+2)KA3(n+2) + A(n+1)KA2(n+1) + A(n)KA1(n)

+ B(n+2)KB3(n+2) + B(n+1)KB2(n+1) + B(n)KB1(n)

+ C(n+2)KC3(n+2) + C(n+1)KC2(n+1) + C(n)KC1(n)

+ CASIN(n+3)

CASOUT(n+7)

4 x 2-Pixel Convolver — Mode 11

= A(n+3)KA3(n+3) + A(n+2)KA2(n+2) + A(n+1)KA1(n+1)

+ A(n)KC3(n+3) + B(n+3)KB3(n+3) + B(n+2)KB2(n+2)

+ B(n+1)KB1(n+1) + B(n)KC1(n+1)

+ CASIN(n+4)

Video Imaging Products

4

08/16/2000–LDS.2250-L

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