PSD301 데이터 시트보기 (PDF) - Waferscale Integration

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PSD301

Low Cost Microcontroller Peripherals

Waferscale Integration 

10.0

I/O Port

Functions

(cont.)

PSD3XX Family

10.2.2 Port A (PA0-PA7) in Non-Multiplexed Address/Data Mode

In this mode, Port A becomes the low-order data bus byte of the chip. When reading an

internal location, data is presented on Port A pins to the MCU. When writing to an internal

location, data present on Port A pins from the MCU is written to the desired location.

Figure 5A. Port A Pin Structure

I

N

T

E

R

READ DATA

N

A

L

A

WRITE DATA CK

D

DFF

D

R

DR

/

D

ALE

G

A

LATCH

T

D

A

R

B

U

S

A

D

0

/

A

D

7

RESET

READ DIR

D DIR

WRITE DIR CK FF

R

MCU

I/O

OUT

LATCHED

ADDR OUT

ADn/ Dn

READ PIN

CMOS / OD(1)

PORT A PIN

MUX

ENABLE

CONTROL

NOTE: 1. CMOS/OD determines whether the output is open drain or CMOS.

Figure 5B. Port A Track Mode

CONTROL

DECODER

INTERNAL

READ

WR or R/W

RD / E

AD0 –AD7

ALE or AS

CSADIN

INTERNAL

ALE

AD8– AD15

A16 – A19

A11– A15

LATCH

CSADOUT1

PAD

CSADOUT2 (1)

I

PA0 – PA7

O

NOTE: 1. The expression for CSADOUT2 must include the following write operation cycle signals:

For CRRWR = 0, CSADOUT2 must include WR = 0.

For CRRWR = 1, CSADOUT2 must include E = 1 and R/W = 0.

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