LU5X34F 데이터 시트보기 (PDF) - Agere -> LSI Corporation

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LU5X34F

Quad Gigabit Ethernet Transceiver

Agere -> LSI Corporation 

Preliminary Data Sheet

July 2000

LU5X34F

Quad Gigabit Ethernet Transceiver

Test Modes (continued)

Table 18. Test Modes (continued)

Global

BYPPLL

0

Local Test Configuration

TEST1 TEST2 TEST3 TEST4

0

0

1

0

0

0

0

0

1

0

0

0

0

0

1

X

X

1

C-0

1

X

X

0

C-0

Global

TEST5

Output

X

Output

C-90

C-90

OPERATION

Transmitter is held in reset. BYPPLL

overrides this reset. Analog PLL feed-

back signal viewed at TEST5 pin.

Transmitter and receiver are held in

reset. RX[9:0] output is from digital fil-

ter, not the serial data.

Transmitter and receiver are held in

reset. RX[9:0] output is from digital fil-

ter, not the serial data. Analog PLL

feedback signal viewed at TEST5 pin.

Analog PLL is bypassed for low speed

functional test. A low-speed clock is

input to TEST4, and a quadrature clock

is applied to TEST5. Frequency of

clocks is 5X REFCLK, but here REF-

CLK is lowered to about 1 MHz.

Analog PLL is bypassed for low-speed

functional test. A low-speed clock is

input to TEST4, and a quadrature clock

is applied to TEST5. Frequency of

clocks is 5X REFCLK, but here REF-

CLK is lowered to about 1 MHz.

RX[9:0] output is from digital filter, not

the serial data.

Lucent Technologies Inc.

23

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