VSC7185 데이터 시트보기 (PDF) - Vitesse Semiconductor
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VSC7185 Datasheet PDF : 18 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Quad Transceiver for
Gigabit Ethernet and Fibre Channel
Preliminary Data Sheet
VSC7185
Table 7: Pin Description
Pin
N1, N2
N3, N4
M1
J1, J2
J3, J4
H1
G16, G15
G14, H17
H16
L17, L16
L15, L14
M17
K17
R1
R2
P3
P2
P17
P16
R5, P5
R7, P7
P11, R11
P13, R13
Name
TX00, TX01
TX02 TX03
TX04
TX10, TX11
TX12, TX13
TX14
TX20, TX21
TX22, TX23
TX24
TX30, TX31
TX32, TX33
TX34
TC
RFCT
RFC+
RFC-
RFCM
RSYN
RFCO (NC)
SO0+, SO0-
SO1+, SO1-
SO2+, SO2-
SO3+, SO3-
Description
INPUT - SSTL-2: 5-Bit Transmit bus for Channel 0. Input timing is referenced to the
TC input. TX00 is transmitted first.
INPUT - SSTL-2: 5-Bit Transmit Bus for Channel 1. Input timing is referenced to the
TC input. TX10 is transmitted first.
INPUT - SSTL-2: 5-Bit Transmit Bus for Channel 2. Input timing is referenced to the
TC input. TX20 is transmitted first.
INPUT - SSTL-2: 5-Bit Transmit Bus for Channel 3. Input timing is referenced to the
TC input. TX30 is transmitted first.
INPUT - SSTL-2: Transmit Low-Speed Input Clock for TXi(0:4).
INPUT - TTL: TTL Reference Clock. The rising edge of RFCT provides the reference
clock, at 1/10th or 1/20th of the baud rate (depending on RFCM) to the clock
multiplying PLL. If RFCT is used, pull RFC+ HIGH and leave RFC- open. If RFC+
and RFC- are used, pull RFCT HIGH or leave open.
INPUT - PECL: PECL Differential Reference Clock. The rising edge of RFC+ (falling
edge of RFC-) provides the reference clock, at 1/10th or 1/20th of the baud rate
(depending on RFCM) to the clock multiplying PLL. If RFC+ and RFC- are used, pull
RFCT HIGH or leave open. If RFCT is used, pull RFC+ HIGH and leave RFC- open.
INPUT - SSTL-2: Reference Clock Mode Select. When LOW, REF is at 1/20th of the
transmit baud rate (e.g., 62.5MHz for 1.25Gb/s). When HIGH, REF is at 1/10th the
baud rate (e.g., 125MHz for 1.25Gb/s).
INPUT - SSTL-2: Receive Byte Clock Synchronization Control. When LOW,
RXi(0:4) and SYNi data transitions are centered around RCi(0:1) clock transitions.
When HIGH, RXi(0:4) and SYNi data transitions are aligned with RCi(0:1) transitions,
so that receive interface timing resembles transmit interface timing.
OUTPUT - TTL: This is an identical copy of the transmit baud rate clock divided by
10. (NC for HDMP-1685 socket.)
OUTPUT - Differential PECL: AC-Coupling recommended.
These pins output the serialized transmit data for Channel x when PLUP is LOW.
When PLUP is HIGH, SO+ is HIGH and SO- is LOW.
Page 12
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52324-0, Rev. 3.0
8/28/00
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