UT1750AR(2003) 데이터 시트보기 (PDF) - Aeroflex UTMC
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UT1750AR Datasheet PDF : 55 Pages
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Pop instructions. When the UT1750AR is operating in the RISC
mode, it pre-increments (pops) and post-decrements (pushes)
the SP. In the 1750 mode, the UT1750AR pre-increments (pops) 7
RE
and post-increments (pushes) the SP.
The programmer accesses the SP by using local I/O commands [0]
to Load and Store the Stack Pointer.
6
OE
The System Status Register
Figure 8. The System Status Register provides additional status
information on the UT1750AR’s internal signals, including the of
status of the internal UART. The bit definitions for STATUS
are given below.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5
FE
M
T
I
RO F P C TD
C P ZNVJ M
B
E
EE EEN ER
E
E
4
PE
MSB
this
LSB
Figure 8. The System Status Register (STATUS)
with
Bit Definitions
All bits in the System Status Register are active high. The values 3
CN
in the brackets indicate the power-up state.
BIT
NUMBER MNEMONIC
15
C
DESCRIPTION
Carry. This conditional
status is set if a carry
generated. [0]
the
2
TBE
14
P
13
Z
is
Positive. This conditional
status is set if the result of
operation is positive. [0]
1
TE
Zero. This conditional status
set if the result of an operation
is equal to zero. [0]
12
N
11
V
Negative. This conditional
status is set if the result of an 0
DR
operation is negative. [0]
Overflow. This conditional
the
status is set when an overflow
condition occurs. [0]
10
J
Normalized. Thisconditional
status is set as the result of a
long instruction. [0]
9
IE
Interrupts enabled. [0]
8
MME
Memory Management
enabled. [0]
Receiver Error. This bit is the
logical OR combination of the
OE, FE, and PE status bits.
Overrun Error. When active,
this bit indicates that at least
one data word was lost because
the Data Ready (DR is bit 0
the STATUS) signal was
active twice consecutively
without an RBR read. [0]
Framing Error. When active,
this bit indicates a stop bit was
missing from the serial
transmission. [0]
Parity Error. When active,
bit indicates the serial
transmission was received
the incorrect parity. [0]
MIL-STD-1750A Console
Enabled. When active, this bit
indicates the CONSOLE
discrete input is active.
CONSOLE active sets bit 3 in
System Status Register.
UART Transmitter Buffer
Empty. This bit indicates the
Transmitter Buffer Register is
empty and ready for data. [0]
UART Transmitter Empty.
This bit is low while the
UART is transmitting data and
goes high when the
transmission is complete. [0]
UART Data Ready. This
active-high signal indicates
UART received a serial data
word and this data is
available. [0]
15
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