APU0065QE-TY 데이터 시트보기 (PDF) - Anpec Electronics

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APU0065QE-TY

40 CH Driver for Dot Matrix LCD

Anpec Electronics 

APU0065 PRELIMINARY

PIN DESCRIPTION-QFP100

PAD (NO.)

INPUT/

OUTPUT

NAME

V EE ( 3 3 )

VDD(25)

V SS ( 3 6 )

V1 ~ V6

(46 ~ 51)

M (42)

CL1, CL2

(34, 35)

Power

Power

Power

Input

Input

Input

Negative Supply Voltage

Operating Voltage

Operating Voltage

Bias Voltage

Altemated signal for LCD

driver output

Data shift / latch clock

DESCRIPTION

For LCD driver circuit(0 ≥ ≥ VEE VDD - 1 0 V)

For logical circuit (+5V± 10%, +3V± 10%)

0V (GND)

Bias Voltage level for LCD drive

This is the signal for LCD twisting

These signal control the shift and latch of

driver. More detail scription in next lineF C S.

If FCS equals to VSS , Part1 and Part2 both are segment mode.

If FCS equals to VDD , Part1 is segment mode but Part2 is

common mode .

INTERFACE

Power Supply

Power Supply

Power Supply

Power Supply

Controller

Controller

FCS (45)

Input

Mode selection

Mode

CL1

CL2

M

Segment latch

shift

M

Controller

Common shift

latch

M

SHL1 (43)

Input

Shifting direction control

signal of Part1

Selection of the shift directon of Part 1 shift register

SHL1 DL1 DR1

VDD output input

V SS

input output

DL1, DR1

(37, 38)

SC1 ~ SC20

SHL2 (44)

Input

Output

Output

Input

Data interface

LCD driver

Shifting direction control

signal of Part2

Data input / output of Part1 shift register

LCD driver output of Part1

Selection of the shift directon of Part 2 shift register

SHL2

VDD

V SS

DL2 DR2

output Input

Input output

DL2, DR2

(39, 40)

SC21 ~ SC40

Input

Output

Output

Data interface

LCD driver

Data input / output of Part 2 shift register

LCD driver output of Part2

Controller

Controller

or

APU0063

LCD

Controller

Controller

or

APU0063

LCD

Note : Input pin can not be floated, or it will cause large leakage current.

Copyright  ANPEC Electronics Corp.

3

Rev. A.07 - FEB., 2002

www.anpec.com.tw

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