DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

UT1553 데이터 시트보기 (PDF) - Aeroflex UTMC

부품명
상세내역
제조사
UT1553
UTMC
Aeroflex UTMC UTMC
UT1553 Datasheet PDF : 40 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
3.4 Control Register (CTL)
The CTL provides the host with the ability to control four functions: (1) programming the bits in 1553 status word; (2) masking
the End of Receive/Transmit message activity interrupt (output pin EORT); (3) enabling and selecting the channel for the self-
test; and (4) selecting the active 1553 channel. The definition of the 1553 status word bits in the CTL is different when the
RTMP is operating in the 1553A mode (PRA/B = 1) as opposed to the1553B mode (PRA/B = 0). Figure 6 shows the bit
definitions in the CTL for the 1553A mode; figure 7 shows the definition for the 1553B mode.
The host determines the CTL functions status by reading the CTL Register.
CTL Bit Definitions - 1553A Mode
Bit 15
CHAEN [0]
Channel A Enable. When CHAEN = 1, the RTMP responds to a 1553 command word or mode
code on bus Channel A. CHAEN = 0 disables the RTMP from responding to 1553 command word
or mode code on 1553 bus Channel A.
Bit 14
CHBEN [0]
Channel B Enable. When CHBEN = 1, the RTMP responds to a 1553 command word or mode
code on bus Channel B. CHBEN = 0 disables the RTMP from responding to 1553 command word
or mode code on 1553 bus Channel B. Disable for internal self-test.
Bit 13
STEN [0]
Self-Test Enable. STEN enables the RTMP’s internal self-test.
Bit 12
STCS [0]
Self-Test Channel Select. If the host has enabled an RTMP self-test (STEN = 1), STCS selects
the RTMP receiver channel to test. STCS = 1 selects Channel A, and STCS = 0 selects Channel B.
Bit 11
IM1 [0]
Interrupt Mask One. If IM1 = 1, the EORT interrupt output is active at the end of 1553 receive
command memory activity. IM1 = 0 masks this interrupt function.
Bit 10
IM2 [0]
Interrupt Mask Two. If IM2 = 1, the EORT interrupt output is active at the end of 1553 transmit
command memory activity. IM2 = 0 masks this interrupt function.
Bit 9
SWB10 [0]
Status Word Bit 10. When the host sets this bit, SWB10 = 1, the bit in the RTMP’s status word
that is transmitted during bit time ten is set (see figure 30 for status word bit time definitions).
The bits in the status word are system-defined in MIL-STD-1553A.
Bit 8
SWB11 [0]
Status Word Bit 11. When the host sets this bit (SWB11 = 1), the bit in the RTMP’s status word
transmitted during bit time 11 is set.
Bit 7
SWB12 [0]
Status Word Bit 12. When the host sets this bit (SWB12 = 1), the bit in the RTMP’s status word
transmitted during bit time 12 is set.
Bit 6
SWB13 [0]
Status Word Bit 13. When the host sets this bit (SWB13 = 1), the bit in the RTMP’s status word
transmitted during bit time 13 is set.
Bit 5
SWB14 [0]
Status Word Bit 14. When the host sets this bit (SWB14 = 1), the bit in the RTMP’s status word
transmitted during bit time 14 is set.
Bit 4
SWB15 [0]
Status Word Bit 15. When the host sets this bit (SWB15 = 1), the bit in the RTMP’s status word
transmitted during bit time 15 is set.
Bit 3
SWB16 [0]
Status Word Bit 16. When the host sets this bit (SWB16 = 1), the bit in the RTMP’s status word
transmitted during bit time 16 is set.
Bit 2
SWB17 [0]
Status Word Bit 17. When the host sets this bit (SWB17 = 1), the bit in the RTMP’s status word
transmitted during bit time 17 is set.
Bit 1
SWB8 [0]
Status Word Bit 18. When the host sets this bit (SWB18 = 1), the bit in the RTMP’s status word
transmitted during bit time 18 is set.
Bit 0
TFLG
Terminal Flag. TFLG = 1 sets the Terminal Flag bit in the 1553A status word. TFLG = 0 resets
the Terminal Flag bit in the 1553A status word.
RTMP-13

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]