IS62V6416BLL-12K 데이터 시트보기 (PDF) - Integrated Silicon Solution
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IS62V6416BLL-12K Datasheet PDF : 11 Pages
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IS62V6416BLL
ISSI ®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-100
-120
Symbol
Parameter
Min. Max.
Min. Max.
Unit
tWC
Write Cycle Time
100
—
120
—
ns
tSCS
CS to Write End
80
—
100
—
ns
tAW
Address Setup Time to Write End
80
—
100
—
ns
tHA
Address Hold from Write End
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
ns
tPWB
LB, UB Valid to End of Write
80
—
100
—
ns
tPWE1,2
WE Pulse Width
80
—
100
—
ns
tSD
Data Setup to Write End
60
—
60
—
ns
tHD
Data Hold from Write End
0
—
0
—
ns
tHZWE(3)
WE LOW to High-Z Output
0
30
0
—
ns
tLZWE(3)
WE HIGH to Low-Z Output
5
—
5
—
ns
Notes:
1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof1.5V,inputpulselevelsof0to3VandoutputloadingspecifiedinFigure1.
2. Theinternalwritetimeisdefinedbytheoverlapof CSLOWand UBorLB,andWE LOW. AllsignalsmustbeinvalidstatestoinitiateaWrite,butanyonecangoinactiveto
terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
3. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.
WRITE CYCLE NO. 1(1,2) (CS Controlled, OE = HIGH or LOW)
t WC
ADDRESS
t SA
CS
WE
VALID ADDRESS
t SCS
t HA
t AW
t PWE1
t PWE2
t PBW
UB, LB
DOUT
DATA UNDEFINED
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DIN
DATAIN VALID
UB_CSWR1.eps
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS and WE inputs and at least one of
the LB and UB inputs being in the LOW state.
2. WRITE = (CS) [ (LB) = (UB) ] (WE).
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/00
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