MCM63P818TQ100R 데이터 시트보기 (PDF) - Motorola => Freescale
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MCM63P818TQ100R
Motorola => Freescale
MCM63P818TQ100R Datasheet PDF : 20 Pages
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APPLICATION INFORMATION
SLEEP MODE
A sleep mode feature, the ZZ pin, has been implemented
on the MCM63P736 and MCM63P818. It allows the system
designer to place the RAM in the lowest possible power
condition by asserting ZZ. The sleep mode timing diagram
shows the different modes of operation: Normal Operation,
No READ/WRITE Allowed, and Sleep Mode. Each mode has
its own set of constraints and conditions that are allowed.
Normal Operation: All inputs must meet setup and hold
times prior to sleep and tZZREC nanoseconds after
recovering from sleep. Clock (K) must also meet cycle, high,
and low times during these periods. Two cycles prior to
sleep, initiation of either a read or write operation is not al-
lowed.
No READ/WRITE: During the period of time just prior to
sleep and during recovery from sleep, the assertion of either
ADSC, ADSP, or any write signal is not allowed. If a write
operation occurs during these periods, the memory array
may be corrupted. Validity of data out from the RAM can not
be guaranteed immediately after ZZ is asserted (prior to be-
ing in sleep).
Sleep Mode: The RAM automatically deselects itself. The
RAM disconnects its internal clock buffer. The external clock
may continue to run without impacting the RAMs sleep cur-
rent (IZZ). All inputs are allowed to toggle — the RAM will not
be selected and perform any reads or writes. However, if in-
puts toggle, the IZZ (max) specification will not be met.
NON–BURST SYNCHRONOUS OPERATION
Although this BurstRAM has been designed for PowerPC–
and Pentium–based systems, these SRAMs can be used in
other high speed L2 cache or memory applications that do
not require the burst address feature. Most L2 caches de-
signed with a synchronous interface can make use of the
MCM63P736 and MCM63P818. The burst counter feature of
the BurstRAMs can be disabled, and the SRAMs can be con-
figured to act upon a continuous stream of addresses. See
Figure 6.
CONTROL PIN TIE VALUES (H ≥ VIH, L ≤ VIL)
Non–Burst
ADSP ADSC ADV SE1 LBO
Sync Non–Burst,
Pipelined SRAM
H
L
H
L
X
NOTE: Although X is specified in the table as a don’t care, the pin
must be tied either high or low.
K
ADDR
W
G
DQ
A
B
C
D
E
F
G
H
Q(A)
Q(B)
Q(C)
Q(D)
D(E)
D(F)
D(G)
D(H)
READS
Figure 6. Configured as Non–Burst Synchronous SRAM
WRITES
MCM63P736•MCM63P818
18
MOTOROLA FAST SRAM
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