RM5231 데이터 시트보기 (PDF) - PMC-Sierra

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RM5231

Microprocessor with 32-Bit System Bus

PMC-Sierra 

RM5231™ Microprocessor with 32-bit System Bus Data Sheet

Released

Figure 5 Kernel Mode Virtual Addressing (32-bit)

0xFFFFFFFF Kernel virtual address space

(kseg3)

0xE0000000 Mapped, 0.5 GB

0xDFFFFFFF Supervisor virtual address space

(ksseg)

0xC0000000 Mapped, 0.5 GB

0xBFFFFFFF Uncached kernel physical address space

(kseg1)

0xA0000000 Unmapped, 0.5 GB

0x9FFFFFFF Cached kernel physical address space

(kseg0)

0x80000000 Unmapped, 0.5 GB

0x7FFFFFFF User virtual address space

(kuseg)

Mapped, 2.0 GB

0x00000000

3.14 Joint TLB

For fast virtual-to-physical address translation, the RM5231 uses a large, fully associative TLB

that maps 96 virtual pages to their corresponding physical addresses. As indicated by its name, the

joint TLB (JTLB) is used for both instruction and data translations. The JTLB is organized as 48

pairs of even-odd entries, and maps a virtual address and address space identifier into the large, 64

GB physical address space.

Two mechanisms are provided to assist in controlling the amount of mapped space and the

replacement characteristics of various memory regions. First, the page size can be configured, on a

per-entry basis, to use page sizes in the range of 4 KB to 16 MB (in multiples of 4). The CP0 Page

Mask register is loaded with the desired page size of a mapping, and that size is stored into the

TLB along with the virtual address when a new entry is written. Thus, operating systems can

create special purpose maps; for example, an entire frame buffer can be memory mapped using

only one TLB entry.

The second mechanism controls the replacement algorithm when a TLB miss occurs. The

RM5231 provides a random replacement algorithm to select a TLB entry to be written with a new

mapping. However, the processor also provides a mechanism whereby a system specific number of

mappings can be locked into the TLB, thereby avoiding random replacement. This mechanism

allows the operating system to guarantee that certain pages are always mapped for performance

reasons and for deadlock avoidance. This mechanism also facilitates the design of real-time

systems by allowing deterministic access to critical software.

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

17

Document ID: PMC-2002165, Issue 1

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