PM5352 데이터 시트보기 (PDF) - PMC-Sierra

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PM5352

SATURN USER NETWORK INTERFACE (STAR)

PMC-Sierra 

DATA SHEET

PMC-1990421

ISSUE 2

PM5352 S/UNI STAR

SATURN USER NETWORK INTERFACE 155 (STAR)

6 PIN DESCRIPTION

6.1 Line Side Interface Signals

Pin Name

REFCLK

RXD+

RXD-

Type

Input

Pin

No.

AC5

Differential AA1

PECL Y2

inputs

Function

The reference clock input (REFCLK) must provide a

jitter-free 19.44 MHz reference clock. It is used as

the reference clock by both clock recovery and

clock synthesis circuits.

When the WAN Synchronization controller is used,

REFCLK is supplied using a VCXO. In this

application, the transmit direction can be looped

timed to any of the line receivers in order to meet

wander transfer and holdover requirements.

.

The receive differential data inputs (RXD+, RXD-)

contain the NRZ bit serial receive stream. The

receive clock is recovered from the RXD+/- bit

stream. Please refer to the Operation section for a

discussion of PECL interfacing issues.

SD

RCLK

Single-

Ended

PECL

Input

Output

W3

AB14

The Signal Detect pin (SD) indicates the presence

of valid receive signal power from the Optical

Physical Medium Dependent Device. A PECL high

indicates the presence of valid data and a PECL

low indicates a loss of signal. It is mandatory that

SD be terminated into the equivalent network that

RXD+/- is terminated into.

.

The receive byte clock (RCLK) provides a timing

reference for the S/UNI-STAR receive outputs.

RCLK is a divide by eight of the recovered line rate

clock (19.44 MHz).

.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 11

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