AS1700-NPN 데이터 시트보기 (PDF) - Astec Semiconductor => Silicon Link
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AS1700-NPN Datasheet PDF : 20 Pages
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AS17xx
Semicustom Bipolar Array
Signal & common coupling: If high frequency
signals are present which have large amplitude
swings, these lines should be separated as much
as possible with respect to their pin locations
because of inductive or capacitive coupling be-
tween their pins and bonding wires.
Another coupling problem arises when there are
long metal lines. For example, if there is a com-
mon ground line for both the input and output of
an amplifier, the fluctuating current from the
output could cause a voltage drop along the line
that could effect the input. This coupling could
cause distortion or oscillations. The solution to
this problem is to run two separate ground lines
to the ground pad.
Resistor ratioing: Where matched resistor val-
ues or precise ratios are required, identical resis-
tor constructs and orientations should be used.
Identical resistors orientated 90° to each other
may have different values due to directionally
dependent fabrication and packaging tolerances.
Component interconnection: We recommend
numbering the components on the circuit sche-
matic and using these numbers on the layout.
Work on only one circuit block at a time and leave
the block interconnections until all the blocks are
finished. Start the layout by selecting several
components of a block and placing them on the
layout; sketch their interconnections and work
outward marking the schematic as you go.
Metal routing: The metal routing can be sketched
on the layout sheet taking into account the de-
sign rule considerations as follows:
Design Rules:
• Minimum metal width = 8 microns
• Minimum spacing between metal
traces = 8 microns
• Current capacity of metal trace = 4 mA
per micron of width
• Metal line to pad (active) = 24 microns
(note: metal resistance ≈ 0.02 Ω
per square)
The area around the outside of the chip has a
metalized ring with numerous contacts to the
substrate. The substrate must be connected to
the most negative potential in the circuit. When
laying out the circuit, the ground conductors
should lead inward from the outer ring. There are
several N-layer contacts for the different resistor
tub areas that must be connected to the most
positive potential in the circuit to maintain
isolation.
Bonding pads: The rules for bonding pad lay-
outs are very simple. You must be able to draw
a straight line from a bonding pad to its pin
without crossing any other wires, and the pads
should be evenly spaced around the chip. The
pin assignments are arbitrary, but they should be
organized such that the pin numbers correspond
to the pads in a counter-clockwise rotation around
the chip, and not some random pattern that
would cause bonding wires to cross each other.
Layout sheets (500x) are available upon re-
quest for final layout, and are used to make the
metal interconnect mask and check spacing rules.
We recommend that the metal interconnect be
done on a clear film over the layout sheet with
erasable markers before making the final layout.
This will allow for modifications to be made with
a minimum amount of effort.
ASTEC Semiconductor
130
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