M41T00 데이터 시트보기 (PDF) - STMicroelectronics

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M41T00

Serial real-time clock

STMicroelectronics 

Device operation

M41T00

2.9

WRITE mode

In this mode the master transmitter transmits to the M41T00 slave receiver. Bus protocol is

shown in Figure 10. Following the START condition and slave address, a logic '0' (R/W = 0)

is placed on the bus and indicates to the addressed device that word address An will follow

and is to be written to the on-chip address pointer. The data word to be written to the

memory is strobed in next and the internal address pointer is incremented to the next

memory location within the RAM on the reception of an acknowledge clock. The M41T00

slave receiver will send an acknowledge clock to the master transmitter after it has received

the slave address and again after it has received the word address and each data byte (see

Figure 7).

Figure 10. WRITE mode sequences

BUS ACTIVITY:

MASTER

SDA LINE

S

WORD

ADDRESS (An)

DATA n

BUS ACTIVITY:

SLAVE

ADDRESS

DATA n+1

DATA n+X P

AI00591

2.10 Data retention mode

With valid VCC applied, the M41T00 can be accessed as described above with READ or

WRITE cycles. Should the supply voltage decay, the M41T00 will automatically deselect,

WRITE protecting itself when VCC falls (see Figure 11).

Figure 11. Power down/up mode AC waveforms

VCC

VSO

tPD

SDA

SCL

DON'T CARE

tREC

AI00596

Table 3. RTC power down/up ac characteristics

Symbol

Parameter(1)(2)

Min

Typ

Max

tPD

SCL and SDA at VIH before power down

0

trec

SCL and SDA at VIH after power up

10

1. Valid for ambient operating temperature: TA = -40 to 85°C; VCC = 2.0 to 5.5 V (except where otherwise noted).

2. VCC fall time should not exceed 5 mV/µs.

Unit

ns

µs

12/25

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