CDP68HC68S1 데이터 시트보기 (PDF) - Intersil

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CDP68HC68S1

Serial Multiplexed Bus Interface

Intersil 

CDP68HC68S1

the SBl chip should also be connected together, as shown in

Figure 11. Synchronization of the data that is transferred

between the user microcomputer and the SBl chip is done by

the SCK signal which is provided by the user microcomputer.

The Slave Select (SS) pin on the user microcomputer must

be wired high or forced high whenever the SBl chip is

selected.

The user microcomputer should configure its SPl port for

master mode operation, SCK low polarity, and data transfer

on first edge (i.e. CPOL = 0, CPHA = 1 for 68HC05 micro-

computers).

The SBI chip must be chip selected either by a user micro-

computer output signal or by permanent wiring of its pins. To

select the Buffered SPl mode, set the MODE pin and the CS

pin to logic zero. This is required in order to transfer data

between the SBl chip and the user microcomputer. However,

in the Buffered SPl mode, since the MCU is operating as a

master and controls the SPI port, chip selection is only

required during when the SPl transfers are actually occurring.

MCU

MOSI

MISO

SCK

SS

PAO

PA1

SBIC

XMIT BUS+

REC

BUS-

SCK

+VDD

IDLE

CONTROL

MODE CS

DIFFERENTIAL

BUS

+VDD

FIGURE 11. USING THE BUFFERED SPI MODE

Buffered SPI Mode, Software

The principle difference between the Buffered SPI mode and

the normal SPl mode is the use of a 2 byte internal buffer.

Also, the Buffered SPl mode allows the user microcomputer

to operate in the master mode, instead of the slave mode,

which allows high speed transferring of data between the

SBl chip’s buffer and the user microcomputer.

For typical operation, the user microcomputer loads the

SBl’s 2 byte buffer, at a high speed, using its SPl interface.

The 68HC05’s SPl Finished flag (SPlF), and optionally its

associated interrupt, may be used by the user microcom-

puter to know when the transfer of a byte between the user

microcomputer and the SBl chip is complete. Then it signals

the SBl chip, by pulling its CONTROL line low, to transmit the

data in the buffer onto the differential bus.

The SBl chip, at a differential bus speed, then attempts to

transmit the buffered data onto the bus. During this attempt,

the SBl chip will receive two reflected bytes of data back

from the bus, store them in the buffer and then disable the

buffer from receiving further data from the differential bus

until this received data is later unloaded by the user micro-

computer at high SPl transfer speeds. The MCU should also,

at this time, simultaneously load the next 2 bytes of data to

be transmitted into the buffer.

While it is transmitting and receiving the 2 bytes of data on

the differential bus the SBl chip will not allow transfer of data

to and from the user microcomputer. In fact, the SBl chip

does not need to be chip selected during this time.

The bus will override the user microcomputer if incoming

data is received during the time when the user microcom-

puter is performing a data transfer, after having unloaded the

previous 2 bytes. The data from the differential bus will be

loaded into the SBlC buffer, while the data from the user

microcomputer will be lost. The data that the user microcom-

puter will receive during this transfer, is undefined. The user

microcomputer has no way of knowing its transfer has been

aborted unless it either monitors the CONTROL signal for a

rising transition or by detecting that CONTROL was not high

at completion of the SPl transfer.

Monitoring the Control Signal

The user microcomputer should monitor the CONTROL sig-

nal on the SBl chip, in order to determine whether it is

actively transmitting or receiving data. The CONTROL signal

is used to determine who has access to the 2 byte buffer. Dur-

ing data reception or transmission to the differential bus by the

SBlC its CONTROL pin is low signifying that the differential

bus now has access to the SBlC and the MCU is locked out

from accessing the SBlC. Then when 2 bytes of data have

been received from the differential bus, the SBl chip will pull its

CONTROL line high, signaling to the MCU that the MCU can

now access the SBlC’s 2 byte buffer. The MCU may now read

the 2 bytes received and simultaneously transmit two more

bytes (if desired) by performing a 2 byte transfer (a swap of

data), via the MCU SPl port, with the SBlC; then the MCU

pulls the SBlC’s CONTROL pin low to transmit the two new

bytes. The CONTROL pin will remain latched low (by the

SBlC) until the two new bytes are transmitted.

The user microcomputer should also monitor the IDLE signal

in order to accurately know when the bus is idle or when bus

arbitration is occurring, when a received message has finished,

and when the next bytes to be received are the beginning bytes

of a new message. Preferably, the user microcomputer’s exter-

nal interrupt should be set up to edge detect falling IDLE and

rising CONTROL transitions.

When the CONTROL pin goes high, it signals that the buffer is

full and that the user microcomputer currently has access. When

the IDLE pin goes low, it is signaling that the current message

has been completed, and an MCU may now arbitrate for the bus.

Size of Messages that can be Transmitted or Received

In the Buffered SPI mode, the user microcomputer can only

send messages in 2 byte multiples. Transmitting messages

with an odd number of bytes, to other microcomputers on the

bus, is NOT supported by the SBl chip in Buffered SPl mode.

However, reception of any number of bytes is supported.

In the Buffered SPl mode, the user microcomputer can receive

messages of any length. For odd length messages, the user

microcomputer must know when the message is finished either

from the message ID byte or via the IDLE signal. Since the SBl

chip will give no indication as to whether the buffer contains one

or 2 bytes of information from the bus, the message length

should be contained within the message data bytes.

6-96

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