CDP68HC68S1M 데이터 시트보기 (PDF) - Intersil

부품명

상세내역

제조사

CDP68HC68S1M

Serial Multiplexed Bus Interface

Intersil 

CDP68HC68S1

When a single byte is received from the bus, followed by a

bus idle condition, the SBl chip will, as it normally does when

the buffer has received 2 bytes, set the CONTROL signal

high. It will then relinquish control of the buffer for data trans-

ferral via the user microcomputer, and restrict access to the

buffer from incoming bus data until the 2 byte data transfer

has been completed.

If only 1 byte is received from the bus, the user microcom-

puter will receive it first when performing the 2 byte data

transfer. The second byte received by the user microcom-

puter, during this transfer, is undefined. A 2 byte transfer is

still required in order to return control of the buffer back to

the SBl chip, to gather further incoming data from the bus.

Power On/Reset

The SBI chip is reset internally, at power on. After reset, the

CONTROL pin is set high and IDLE is set low. The buffer

access is set as though 2 bytes have just been received from

the bus. A 2 byte transfer must be performed, via the user

microcomputer, in order to initalize the SBl chip for general

operation.

Sending Messages to Other Microcomputers on the Bus

In order to send a message to other microcomputers on the

bus, while in the Buffered SPl mode, the user microcomputer

should:

1. Monitor the SBlC CONTROL pin to know when it is ok to

perform the 2 byte transfer between the user microcom-

puter and the SBl chip.

2. Perform the 2 byte transfer between the user microcom-

puter and the SBl chip for the first 2 bytes of the message.

3. Pull CONTROL low to tell the SBI chip to start a 2 byte bus

transmit cycle.

4. Wait until CONTROL goes high again indicating that the 2

byte transmit cycle has completed.

5. Perform another 2 byte transfer between the user micro-

computer and the SBl chip, thus giving it the next 2 bytes

to be transmitted and giving the user microcomputer the

2 bytes just received.

6. Compare the just received 2 bytes with the 2 bytes which

were attempted to be transmitted.

7. If the received and last transmitted bytes are equal and

more bytes remain to be sent, then continue the cycle

with step #3.

8. If the received and last transmitted 2 bytes are unequal,

then restart with step #2.

Creating an EOM after a Message Transmission

There must be at least a 10-bit interval of bus idle between

the stop bit of the last byte of one message and the detection

of the start bit of the first byte of the next message. This can

be implemented by either:

1. Including a 10-bit interval time out, via using a timer or

software loop.

2. The user microprocessor can simply wait until it senses

IDLE going low.

Receiving Messages from Other Microcomputers on the

Bus

If the user microcomputer loses arbitration, or if it has no

message to transmit and another microcomputer begins to

send its message onto the bus, the SBI chip will begin to

receive a message from the bus.

The SBlC CONTROL pin will go low at the beginning of the

first data bit that is received from the bus. It will go high

either whenever 2 bytes have been received, or when 1 byte

has been received followed by the bus going idle (i.e. when

IDLE goes low).

The transition of CONTROL from low to high indicates that

the SBI chip has 2 bytes in its internal buffer for the user

microcomputer to retrieve. Whether the SBl chip has

received either 1 or 2 bytes, the user microcomputer must

perform a 2 byte transfer in order to return control of the

buffer back to the SBI chip.

The user microcomputer must detect CONTROL going high

and transfer the 16-bits from the SBl chip before the begin-

ning of the first data bit of the next message or else the bus

will be locked out of accessing the buffer until after both the

next 16-bit transfer is complete and IDLE goes low. Thus, if

there was further incoming data and this did occur, some of

the incoming data may be lost.

Framing Errors

While in the Buffered SPl mode, the SBl chip is capable of

detecting incoming framing errors, however it is unable to

flag this to the user microcomputer. When the SBl chip

detectsaframing error, anyfu rther loading of the SBl chip’s

internal buffer is terminated. The SBI chip essentially quits

receiving data and starts looking for an End Of Message.

Resetting of the framing error will occur upon receiving an

EOM.

Even though the SBl chip can detect framing errors, it can

not flag the user microcomputer that one has occurred.

Since the previously received byte has already been loaded

into the SBI chip’s buffer, the user microcomputer must

determine whether this data is valid. If a framing error occurs

during the first byte of a 2 byte reception, access to the

buffer will be restricted from the user microcomputer until

and EOM occurs. lf a framing error occurs during the second

byte of a 2 byte reception, the user microcomputer will be

given access to the buffer. However, even if the user micro-

computer unloads the buffer, the SBI chip will not load any

further data into the buffer until an EOM occurs. Basically,

when a framing error occurs, no further data is read from the

bus and buffer access is given to the user microcomputer

either immediately or upon an EOM.

One way that the user microcomputer may detect that the

received data is valid, is by using a check sum byte imbed-

ded within each message. Another way would be to compare

the number of bytes received for a particular lD to the num-

ber expected for that ID.

References

Portions of the information contained in this document were

taken and condensed from Chrysler Corporation’s "CCD

USER’S MANUAL" issued April 15,1987.

6-97

Share Link: