ADSP-21061 데이터 시트보기 (PDF) - Analog Devices

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ADSP-21061

Commercial Grade SHARC DSP Microcomputer

Analog Devices 

ADSP-21061/ADSP-21061L

Six channels of DMA are available on the ADSP-21061—four

via the serial ports, and two via the processor’s external port (for

either host processor, other ADSP-21061s, memory or I/O

transfers). Programs can be downloaded to the ADSP-21061

using DMA transfers. Asynchronous off-chip peripherals can

control two DMA channels using DMA request/grant lines

(DMAR1–2, DMAG1–2). Other DMA features include interrupt

generation upon completion of DMA transfers and DMA

chaining for automatic linked DMA transfers.

Serial Ports

The ADSP-21061 features two synchronous serial ports that

provide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices. The serial ports can operate at

the full clock rate of the processor, providing each with a maxi-

mum data rate of up to 50 Mbps. Independent transmit and

receive functions provide greater flexibility for serial communi-

cations. Serial port data can be automatically transferred to and

from on-chip memory via DMA. Each of the serial ports offers

TDM multichannel mode.

The serial ports can operate with little-endian or big-endian

transmission formats, with word lengths selectable from 3 bits

to 32 bits. They offer selectable synchronization and transmit

modes as well as optional μ-law or A-law companding. Serial

port clocks and frame syncs can be internally or externally gen-

erated. The serial ports also include keyword and key mask

features to enhance interprocessor communication.

Multiprocessing

The ADSP-21061 offers powerful features tailored to multipro-

cessor DSP systems. The unified address space (see Figure 4)

allows direct interprocessor accesses of each ADSP-21061’s

internal memory. Distributed bus arbitration logic is included

on-chip for simple, glueless connection of systems containing

up to six ADSP-21061s and a host processor. Master processor

changeover incurs only one cycle of overhead. Bus arbitration is

selectable as either fixed or rotating priority. Bus lock allows

indivisible read-modify-write sequences for semaphores. A vec-

tor interrupt is provided for interprocessor commands. Maxi-

mum throughput for interprocessor data transfer is 500 Mbps

over the external port. Broadcast writes allow simultaneous

transmission of data to all ADSP-21061s and can be used to

implement reflective semaphores.

INTERNAL

MEMORY

SPACE

MULTIPROCESSOR

MEMORY

SPACE

IOP REGISTERS

NORMAL WORD ADDRESSING

(32-BIT DATA WORDS

48-BIT INSTRUCTION WORDS)

SHORT WORD ADDRESSING

(16-BIT DATA WORDS)

INTERNAL MEMORY SPACE

WITH ID = 001

INTERNAL MEMORY SPACE

WITH ID = 010

INTERNAL MEMORY SPACE

WITH ID = 011

INTERNAL MEMORY SPACE

WITH ID = 100

INTERNAL MEMORY SPACE

WITH ID = 101

INTERNAL MEMORY SPACE

WITH ID = 110

BROADCAST WRITE

TO ALL ADSP-21061s

ADDRESS

0x0000 0000

0x0002 0000

0x0004 0000

0x0008 0000

0x0010 0000

0x0018 0000

0x0012 0000

EXTERNAL

MEMORY

SPACE

0x0028 0000

0x0030 0000

0x0038 0000

0x003F FFFF

BANK 0

SDRAM

(OPTIONAL)

ADDRESS

0x0040 0000

MS0

BANK 1

MS1

BANK 2

MS2

BANK 3

MS3

NONBANKED

Figure 4. Memory Map

0x0FFF FFFF

NOTE: BANK SIZES ARE SELECTED BY

MSIZE BITS OF THE SYSCON REGISTER

Rev. D | Page 6 of 52 | May 2013

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