LTC1292 데이터 시트보기 (PDF) - Linear Technology
부품명
상세내역
제조사
LTC1292 Datasheet PDF : 24 Pages
| |||
APPLICATI S I FOR ATIO
LTC1292/LTC1297
21 0
OUTPUT PORT
SERIAL DATA
MPU
2
2
CS
LTC1292
LTC1297
2
CS
LTC1292
LTC1297
2
CS
LTC1292
LTC1297
2 CHANNELS 2 CHANNELS 2 CHANNELS
2-WIRE SERIAL
INTERFACE TO OTHER
PERIPHERALS OR
LTC1292/LTC1297s
LTC1292/7 F06
Figure 6. Several LTC1292/LTC1297s Sharing One 2-Wire Serial Interface
22µF
TANTALUM
VCC
0.1µF
1
8
2 LTC1292 7
3 LTC1297 6
4
5
LTC1292/7 F07
Figure 7. Example Ground Plane
for the LTC1292/LTC1297
use a PC board. The ground pin (Pin 4) should be tied
directly to the ground plane with minimum lead length (a
low profile socket is fine). Figure 7 shows an example of
an ideal LTC1292/LTC1297 ground plane design for a two-
sided board. Of course this much ground plane will not
always be possible, but users should strive to get as close
to this ideal as possible.
Bypassing
For good performance, VCC must be free of noise and
ripple. Any changes in the VCC voltage with respect to
ground during a conversion cycle can induce errors or
noise in the output code. VCC noise and ripple can be kept
below 0.5mV by bypassing the VCC pin directly to the
analog ground plane with a minimum of 22µF tantalum
capacitor and with leads as short as possible. The lead
from the device to the VCC supply also should be kept to a
minimum and the VCC supply should have a low output
impedance such as obtained from a voltage regulator
(e.g., LT323A). For high frequency bypassing a 0.1µF
ceramic disk placed in parallel with the 22µF is
recommended. Again the leads should be kept to a
minimum. Figures 8 and 9 show the effects of good and
poor VCC bypassing.
Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1292/
LTC1297 have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem. If large source resistances are used or if slow
settling op amps drive the inputs, take care to insure that
the transients caused by the current spikes settle completely
before the conversion begins.
HORIZONTAL: 10µs/DIV
Figure 8. Poor VCC Bypassing. Noise and
Ripple Can Cause A/D Errors
CS
VCC
HORIZONTAL: 10µs/DIV
Figure 9. Good VCC Bypassing Keeps
Noise and Ripple on VCC Below 1mV
13
Share Link: 