CXD2719Q 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD2719Q

Single-Chip Dolby Pro Logic Surround Decoder

Sony Semiconductor 

CXD2719Q

5. Microcomputer Interface

[Relevant pins] RVDT, SCK, XLAT, REDY

The CXD2719Q performs the serial audio interface format setting and the coefficient settings such as volume

and filter by serial data from the microcomputer.

(1) Pin Configuration

The four external pins indicated in the table below are assigned to the microcomputer interface.

Symbol

RVDT

SCK

XLAT

REDY

I/O

Function

I Serial data input from microcomputer.

I Shift clock for serial data. Input data from RVDT is taken according to the SCK rise.

I

Interprets the 8 bits of RVDT before this signal rises as transfer mode data, and the

bits before that as address data.

O

Transfer prohibited while at Low level. Transfer enabled at High. This pin is an open

drain, and must be pulled up externally.

Table 5-1. Microcomputer Interface External Pins

(2) Description of Communication Formats

The internal data transfer timing from the microcomputer interface to the coefficient RAM and setup register is

called the SV cycle, and is generated once per 1 LRCK.

The SV cycle is generated immediately preceding the signal processing program, so it has absolutely no effect

on signal processing, and there is no risk of the sound being cut.

Address section + Mode section + Data section

act as one package of data to transfer data from the microcomputer to the CXD2719Q.

[Write] ∗ For coefficient RAM

RVDT

SCK

XLAT

REDY

Address section (8 bits) Mode section (8 bits)

A0

A7 M0

M7

Data section (16 bits)

D0

D15

Fig. 5-1. Example of Communication

– 17 –

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