AS2843D-8 데이터 시트보기 (PDF) - Astec Semiconductor => Silicon Link

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AS2843D-8

Current Mode Controller

Astec Semiconductor => Silicon Link 

AS384x

Current Mode Controller

Resistors R1 and RF set the low frequency gain

and should be chosen to provide the highest pos-

sible gain, without exceeding the unity gain cross-

ing frequency limit of fSW/4. RBIAS, in conjunction

with R1, sets the converterÕs output voltage; but

has no effect on the loop gain/phase response.

There are a few converter design considerations

associated with the error amplifier. First, the val-

ues of the divider network (R1 and RBIAS) should

be kept low in order to minimize errors caused by

the error amplifierÕs input bias current. An output

voltage error equal to the product of the input

bias current and the equivalent divider resis-

tance, can be quite significant with divider values

greater than 5 k½. Low divider resistor values

also help to improve the noise immunity of the

sensitive VFB input.

The second consideration is that the error ampli-

fier will typically source only 0.8 mA; thus, the

value of feedback resistance (RF) should be no

lower than 5 k½ in order to maintain the error

amplifierÕs full output range. In practice, however,

the feedback resistance required is usually much

greater than 5 k½, hence this limitation is nor-

mally not a problem.

Some power supply topologies may require a

more elaborate compensation network. For

example, flyback and boost converters operating

with continuous current have transfer functions

that include a right half plane (RHP) zero. These

types of systems require an additional pole ele-

ment within the compensation network. A

detailed discussion of loop compensation, how-

ever, is beyond the scope of this application note.

1.5 ISENSE current comparator/PWM

latch

The current sense comparator (sometimes

called the PWM comparator) and accompanying

latch circuitry make up the pulse width modula-

tor (PWM). It provides pulse-by-pulse current

sensing/limiting and generates a variable duty

ratio pulse train which controls the output voltage

of the power supply. Included is a high speed

comparator followed by ECL type logic circuitry

which has very low propagation delays and

switching noise. This is essential for high fre-

quency power supply designs. The comparator

has been designed to provide guaranteed perfor-

mance with the current sense input below ground.

The PWM latch ensures that only one pulse is

allowed at the output for each oscillator period.

The inverting input to the current sense com-

parator is internally connected to the level shifted

output of the error amplifier (VE) as discused in

the previous section. The non-inverting input is

the ISENSE input (pin 3). It monitors the switched

inductor current of the converter.

Figure 20 shows the current sense/PWM circuitry

of the AS3842, and associated waveforms. The

output is set high by an internal clock pulse and

remains high until one of two conditions occurs;

1) the oscillator times out (Section 1.3) or 2) the

PWM latch is set by the current sense compara-

tor. During the time when the output is high, the

converterÕs switching device is turned on and

current flows through resistor RS. This produces

a stepped ramp waveform at pin 3 as shown in

Figure 20. The current will continue to ramp up

until it reaches the level of VE at the inverting

input. At that point, the comparatorÕs output goes

high, setting the PWM latch and the output pulse

is then terminated. Thus, VE is a variable refer-

ence for the current sense comparator, and it

controls the peak current sensed by RS on a

cycle-by-cycle basis. VS varies in proportion to

changes in the input voltage/current (inner con-

trol loop) while VE varies in proportion to changes

in the converterÕs output voltage/current (outer

control loop). The two control loops merge at the

current sense comparator, producing a variable

duty ratio pulse train that controls the output of

the converter.

ASTEC Semiconductor

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