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HI5741-EVS(2000) 데이터 시트보기 (PDF) - Intersil

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HI5741-EVS
(Rev.:2000)
Intersil
Intersil Intersil
HI5741-EVS Datasheet PDF : 12 Pages
First Prev 11 12
HI5741
Total Harmonic Distortion, THD, is the ratio of the DAC
output fundamental to the RMS sum of the harmonics. The
first 5 harmonics are included, and an output filter of 1/2 the
clock frequency is used to eliminate alias products.
tone spacing of this pattern (f) is created such that tones 1
through 4 and 5 through 8 are spaced equally, with tones 4
and 5 spaced at 2f. MTPR is measured as the dynamic
range from peak power to peak distortion in the 2f gap.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from a fundamental to the largest harmonically or
non-harmonically related spur. A sine wave is loaded into the
D/A and the output filtered at 1/2 the clock frequency to
eliminate noise from clocking alias terms.
Multi-Tone Power Ratio, MTPR, is the amplitude difference
from peak amplitude to peak distortion (either harmonic or
non-harmonic). An 8 tone pattern is loaded into the D/A. The
Intermodulation Distortion, IMD, is the measure of the
sum and difference products produced when a two tone
input is driven into the D/A. The distortion products created
will arise at sum and difference frequencies of the two tones.
IMD can be calculated using the following equation:
IMD = 2----0----L---o----g------(--R---(-M-R----S-M-----oS---f---AS----mu----m-p----l-ia-t--u-n--d-d---e--D---o-i--ff-f--et--h-r--ee----n-F--c--u-e--n---D-d---ai--s-m--t-o--e--r--nt--i-ot--a-n--l--)-P----r--o----d---u---c---t--s---)
BASEBAND
BIT
STREAM
33 MSPS K9
CLK C11
B11
ENCODER
C10
A11
F10
F9
F11
H11
G11
G9
J11
G10
CONTROLLER
D10
VCC J10
K11
B8
A8
B6
B7
A7
C7
C6
A6
A5
C5
A4
B4
A3
A2
B3
A1
B10
B9
A10
E11
E9
VCC H10
K2
VCC J2
U2
CLK
MOD2
TO RF
MOD1
FILTER UP-CONVERT
U1
STAGE
MOD0
L1
PMSEL DACSTRB
VCC 16 DVCC
IOUT 21
R1
ENPOREG
ENOFREG
ENCFREG
ENPHAC
ENTIREG
INHOFR
INITPAC
INITTAC
TEST
PARSER
BINFMT
C15_MSB
SIN15
SIN14
SIN13
SIN12
SIN11
SIN10
SIN9
SIN8
SIN7
SIN6
SIN5
SIN4
SIN3
SIN2
SIN1
K3
L2
L3
L4
J5
K5
L5
K6
J6
J7
L7
L6
L8
K8
L9
SIN0 L10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
D13 (MSB)
D12
D11
IOUT/
D10
D9
D8 C AMP IN
D7
D6 C AMP OUT
D5
D4
D3
D2
D1 REF OUT
D0 (LSB)
20
24
25
26
23
15 CLK
RSET
C4
C13
C12
C11
R4
50
28 DGND
17
ARET 19
DGND AVSS 27
64
R2
64
C2 0.1µF -5.2V_A
-5.2V_A
C1 0.01µF
R3
976
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
A2
A1
A0
CS
COS15
COS14
COS13
COS12
COS11
COS10
COS9
COS8
COS7
COS6
COS5
COS4
COS3
COS2
COS1
COS0
C2
B1
C1
D1
E3
E2
E1
F2
F3
G3
G1
G2
H1
H2
J1
K1
18 DVEE
-5.2V_D
AVEE 22 -5.2V_A
HI5741
-5.2V_D
L1
10µH
-5.2V_A
L2
10µH
WR
PACI
TICO B2
OES
OEC
HSP45106
FIGURE 27. PSK MODULATOR USING THE HI5741 AND HSP45106 16-BIT NCO
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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