74ACT10M(1997) 데이터 시트보기 (PDF) - STMicroelectronics
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74ACT10M Datasheet PDF : 7 Pages
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74ACT10
TRIPLE 3-INPUT NAND GATE
s HIGH SPEED: tPD = 6.5 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN), VIL = 0.8V (MAX)
s 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 10
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The ACT10 is an advanced high-speed CMOS
TRIPLE 3-INPUT NAND GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology. It is ideal for low
power applications mantaining high speed
PRELIMINARY DATA
B
M
(Plastic Package)
(Micro Package)
ORDER CODES :
74ACT10B
74ACT10M
operation similar to equivalent Bipolar Schottky
TTL.
The internal circuit is composed of 3 stages
including buffer output, which enables high noise
immunity and stable output.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
May 1997
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