AD9830 데이터 시트보기 (PDF) - Analog Devices
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AD9830 Datasheet PDF : 16 Pages
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0
–10
–20
–30
–40
–50
–60
–70
–80
–90
START 0Hz
RBW 1kHz
VBW 3kHz
STOP 25MHz
ST 50 SEC
Figure 17. fMCLK = 50 MHz, fOUT = 16.5 MHz, Frequency
Word = 547AE148
AD9830
Register
Size
FREQ0 REG 32 Bits
FREQ1 REG 32 Bits
PHASE0 REG 12 Bits
PHASE1 REG 12 Bits
PHASE2 REG 12 Bits
PHASE3 REG 12 Bits
Description
Frequency Register 0. This defines
the output frequency, when
FSELECT = 0, as a fraction of the
MCLK frequency.
Frequency Register 1. This de-
fines the output frequency, when
FSELECT = 1, as a fraction of the
MCLK frequency.
Phase Offset Register 0. When
PSEL0 = PSEL1 = 0, the contents
of this register are added to the out-
put of the phase accumulator.
Phase Offset Register 1. When
PSEL0 = 1 and PSEL1 = 0, the
contents of this register are added
to the output of the phase
accumulator.
Phase Offset Register 2. When
PSEL0 = 0 and PSEL1 = 1, the
contents of this register are added
to the output of the phase
accumulator.
Phase Offset Register 3. When
PSEL0 = PSEL1 = 1, the contents
of this register are added to the out-
put of the phase accumulator.
Figure 18. AD9830 Control Registers
A2
A1
A0
Destination Register
0
0
0
FREQ0 REG 16 LSBs
0
0
1
FREQ0 REG 16 MSBs
0
1
0
FREQ1 REG 16 LSBs
0
1
1
FREQ1 REG 16 MSBs
1
0
0
PHASE0 REG
1
0
1
PHASE1 REG
1
1
0
PHASE2 REG
1
1
1
PHASE3 REG
Figure 19. Addressing the Control Registers
D15
MSB
D0
LSB
Figure 20. Frequency Register Bits
D15 D14 D13 D12 D11
D0
X X X X MSB
LSB
X = Don't Care
Figure 21. Phase Register Bits
REV. A
–9–
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