N80C42 데이터 시트보기 (PDF) - Intel

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N80C42

UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLER

Intel 

UPI-C42 UPI-L42

Table 3 Signature Mode Table

Address

Test Code Checksum

Intel Signature

User Signature

Test Signature

Security Byte

UPI-C42 Intel Signature

User Defined UPI-C42 OTP EPROM Space

0

0FH

16H

1EH

10H

11H

12H

13H

14H

15H

1FH or 3FH

20H

21H

22H

3EH

Device

Type

ROM OTP

ROM OTP

OTP

ROM OTP

ROM OTP

ROM OTP

ROM OTP

No of

Bytes

25

2

2

2

2

2

30

ACCESS CODE

The following table summarizes the access codes required to invoke the Sync Mode Signature Mode

and the Security Bit respectively Also the programming and verification modes are included for

comparison

Modes

Control Signals

Data Bus

Port 2

Access Code

Port 1

Programming

Mode

Verification

Mode

Sync Mode

T0 RST SS EA PROG VDD VCC 0 1 2 3 4 5 6 7 0 1 2 3 0 1 2 3 4 5 6 7

0 0 1 HV 1 VDDH VCC

Address

Addr a0 a1 X X X X X X

0 1 1 HV STB VDDH VCC

Data In

Addr

0 0 1 HV 1 VCC VCC

Address

Addr a0 a1 X X X X X X

1 1 1 HV 1 VCC VCC

Data Out

Addr

STB 0 HV 0 X VCC VCC X X X X X X X X X X X X X X X X X X X

High

Signature Prog 0

Mode

0

Verify 0

1

Security Prog 0

Bit Byte

0

Verify 0

1

0 1 HV 1 VDDH VCC

1 1 HV STB VDDH VCC

0 1 HV 1 VCC VCC

1 1 HV 1 VCC VCC

0 1 HV 1 VDDH VCC

1 1 HV STB VDDH VCC

0 1 HV 1 VCC VCC

1 1 HV 1 VCC VCC

Addr (see Sig Mode Table)

Data In

Addr (see Sig Mode Table)

Data Out

Address

Data In

Address

Data Out

000

000

000

000

000

000

000

000

0 1 1 1 1 XX1

NOTE

1 a0 e 0 or 1 a1 e 0 or 1 a0 must e a1

12

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