ISP1581 데이터 시트보기 (PDF) - Philips Electronics

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ISP1581

Universal serial bus 2.0 high-speed interface device

Philips Electronics 

Philips Semiconductors

ISP1581

USB 2.0 HS interface device

Table 13: Interrupt Enable register: bit description…continued

Bit

Symbol

Description

6

IEDMA

A logic 1 enables interrupt upon DMA status change detection.

5

IEHS_STA A logic 1 enables interrupt upon detection of a High Speed

Status change.

4

IERESM

A logic 1 enables interrupt upon detection of a ‘resume’ state.

3

IESUSP

A logic 1 enables interrupt upon detection of a ‘suspend’ state.

2

IEPSOF

A logic 1 enables interrupt upon detection of a Pseudo SOF.

1

IESOF

A logic 1 enables interrupt upon detection of an SOF.

0

IEBRST

A logic 1 enables interrupt upon detection of a bus reset.

9.2.5 DMA Configuration register (address: 38H)

See Section 9.4.3.

9.2.6 DMA Hardware register (address: 3CH)

See Section 9.4.4.

9.3 Data flow registers

9.3.1 Endpoint Index register (address: 2CH)

The Endpoint Index register selects a target endpoint for register access by the

microcontroller. The register consists of 1 byte and the bit allocation is shown in

Table 14. The following registers are indexed:

• Endpoint MaxPacketsize

• Endpoint Type

• Buffer Length

• Data Port

• Short Packet

• Control Function.

For example, to access the OUT data buffer of endpoint 1 via the Data Port register,

the Endpoint Index register has to be written first with 02H.

Table 14: Endpoint Index register: bit allocation

Bit

7

6

5

Symbol

reserved

EP0SETUP

Reset

-

-

0

Bus reset

Access

R/W

R/W

R/W

4

3

2

ENDPIDX[3:0]

00H

unchanged

R/W

1

0

DIR

0

R/W

9397 750 09665

Product data

Rev. 04 — 18 July 2002

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

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