ADM8690AN 데이터 시트보기 (PDF) - Analog Devices

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ADM8690AN

Microprocessor Supervisory Circuits

Analog Devices 

ADM8690/ADM8691/ADM8695

RESET OUTPUT

The internal voltage detector monitors VCC and generates a

RESET output to hold the microprocessor reset line low when

VCC is below 4.65 V. An internal timer holds RESET low for

50 ms (200 ms for the ADM8695) after VCC rises above 4.65 V.

This prevents repeated toggling of RESET, even if the 5 V

power drops out and recovers with each power line cycle.

The crystal oscillator normally used to generate the clock for

microprocessors can take several milliseconds to stabilize.

Because most microprocessors need several clock cycles to

reset, RESET must be held low until the microprocessor clock

oscillator has started. The power-up RESET pulse lasts 50 ms

(200 ms for the ADM8695) to allow for this oscillator start-up

time. If a different reset pulse width is required, a capacitor

should be connected to OSC IN, or an external clock can be

used (see Table 5 and Figure 17 through Figure 20). The manual

reset switch and the 0.1 μF capacitor connected to the reset line

can be omitted if a manual reset is not needed. An inverted,

active high RESET output is also available on the ADM8691/

ADM8695.

POWER-FAIL DETECTOR

The 5 V VCC power line is monitored via a resistive potential

divider connected to the power-fail input (PFI). When the voltage

at PFI falls below 1.3 V, the power-fail output (PFO) drives the

processor’s NMI input low. For example, if a power-fail threshold

of 4.8 V is set with Resistor R1 and Resistor R2 and VCC falls from

4.8 V to 4.65 V, the microprocessor has time to save data into RAM.

An earlier power-fail warning can be generated if the unregulated

dc input to the 5 V regulator is available for monitoring. This

allows more time for microprocessor housekeeping tasks to be

completed before power is lost.

Data Sheet

RAM WRITE PROTECTION

The ADM8691/ADM8695 CEOUT line drives the chip select

inputs of the CMOS RAM. CEOUT follows CEIN as long as VCC

is above the 4.65 V reset threshold.

If VCC falls below the reset threshold, CEOUT goes high, independent

of the logic level at CEIN. This prevents the microprocessor from

writing erroneous data into RAM during power-up, power-down,

brownouts, and momentary power interruptions.

WATCHDOG TIMER

The microprocessor drives the watchdog input (WDI) with an

input/output line. When OSC IN and OSC SEL are unconnected,

the microprocessor must toggle the WDI pin once every 1.6 sec

to verify proper software execution. If a hardware or software fail-

ure occurs such that WDI is not toggled, the ADM8691 issues a

50 ms (200 ms for the ADM8695) RESET pulse after 1.6 sec. This

typically restarts the microprocessor power-up routine. A new

RESET pulse is issued every 1.6 sec until WDI is again strobed.

If a different watchdog timeout period is required, a capacitor

should be connected to OSC IN or an external clock can be

used (see Table 5 and Figure 17 through Figure 20).

The watchdog output (WDO) goes low if the watchdog timer is

not serviced within its timeout period. After WDO goes low, it

remains low until a transition occurs at WDI. The watchdog

timer feature can be disabled by leaving WDI unconnected.

The RESET output has an internal 3 μA pull-up and can either

connect to an open-collector reset bus or directly drive a CMOS

gate without an external pull-up resistor.

Rev. C | Page 18 of 24

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