CXD2428Q
Mode Setting and Operation
1. Horizontal Write
CKI is input after phase comparison with HSYNC input.
PLL frequency division value is set by H SZ WR (standard 38C (hexadecimal)), and HRET is output.
Write start timing is set by H SHIFT.
An ADCK pulse, which is CKI halved, is output.
The enable pulses RYOE and BYOE for R-Y and B-Y A/D converter are output.
HIN
HRET
HWEN
(Internal pulse)
HCR0
RYOE
BYOE
H SZ WR + 2ck
(H SHIFT + 1) × 2ck
CKI
ADCK
RYOE
BYOE
– 11 –