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CXD2428Q 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD2428Q
Sony
Sony Semiconductor Sony
CXD2428Q Datasheet PDF : 16 Pages
First Prev 11 12 13 14 15 16
CXD2428Q
Mode Setting and Operation
1. Horizontal Write
CKI is input after phase comparison with HSYNC input.
PLL frequency division value is set by H SZ WR (standard 38C (hexadecimal)), and HRET is output.
Write start timing is set by H SHIFT.
An ADCK pulse, which is CKI halved, is output.
The enable pulses RYOE and BYOE for R-Y and B-Y A/D converter are output.
HIN
HRET
HWEN
(Internal pulse)
HCR0
RYOE
BYOE
H SZ WR + 2ck
(H SHIFT + 1) × 2ck
CKI
ADCK
RYOE
BYOE
– 11 –

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