R ×5VL
TEST CIRCUITS
VDD
ISS
VDD
R×5VL OUT
SERIES
VSS
GND
FIG. 3 Supply Current Test Circuit
VDD
VSS
VDD Rn
R×5VL OUT
SERIES
GND
Rn:R×5VL××A:100kΩ
R×5VL××C:None
VDET
VSS
FIG. 4 Detector Threshold Test Circuit
VDD
VDD
R×5VL OUT
SERIES
IOUT
+VDS
VSS
GND
VSS
FIG. 5 Nch Driver Output Current Test Circuit
VDD
VSS
VDD
R×5VL××C OUT
SERIES
IOUT
VDD –VDS
GND
VSS
FIG. 6 Pch Driver Output Current Test Circuit
+VDET+2.0V
1.2V
VSS
P.G.
VDD
R×5VL××A OUT
SERIES
GND
+7.0V
ROUT
100kΩ
OUT
COUT
VSS
FIG. 7 Output Delay Time Test Circuit
In Output Delay Time Test Circuit in FIG.7, it's Output Voltage Fall Times (tPHL) and Rise Times (tPLH) are defined
as shown below.
+VDET+2.0V
+VDET+2.0V
Input Voltage
(VDD)
1.2V
GND
Input Voltage
(VDD)
1.2V
GND
7.0V
Output Voltage
3.5V
Output Voltage
+VDET+2.0V
+VDET+2.0V
2
GND
tPHL
tPLH
Nch Open Drain Output
GND
tPHL
tPLH
CMOS Output
15