MSM14Q0230 데이터 시트보기 (PDF) - Oki Electric Industry
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MSM14Q0230 Datasheet PDF : 20 Pages
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Automatic Test Pattern Generation
Oki’s 0.35 µm ASIC technologies support Automatic Test Pattern Generation (ATPG) using full scan-
path design techniques, including the following:
• Increases fault coverage ≥95%
• Uses Synopsys Test Compiler
• Inserts scan structures automatically
• Connects scan chains
• Traces and reports scan chains
• Checks for rule violations
• Generates complete fault reports
• Allows multiple scan chains
• Supports vector compaction
ATPG methodology is described in detail in Oki’s 0.35 µm Scan Path Application Note.
Scan Data In
Scan Select
FD1AS
D
Q
C
SD
SS QN
Combinational Logic
A
B
FD1AS
D
Q
C
SD
SS
QN
Scan Data Out
Figure 6. Full Scan Path Configuration
Floorplanning Design Flow
Oki offers three floorplanning tools for high-density ASIC design. The two main purposes for Oki’s floor-
planning tool are to:
• Ensure conformance of critical circuit performance specifications
• Shorten overall design turnaround time (TAT)
The supported floorplanners are: Cadence DP3, Gambit GFP, and Oki’s internal floorplanner.
In a traditional design approach with synthesis tools, timing violations after prelayout simulation are
fixed by manual editing of the netlist. This process is difficult and time consuming. Also, there is no
physical cluster information provided in the synthesis tool, and so it is difficult to synthesize logic using
predicted interconnection delay due to wire length. Therefore, synthesis tools may create over-optimized
results.
To minimize these problems, Synopsys proposed a methodology called Links to Layout (LTL). Based on
this methodology, Oki developed an interface between Oki’s floorplanners and the Synopsys environ-
ment, called Link Synopsys to Floorplanner (LSF). Because not all Synopsys users have access to the Syn-
opsys Floorplan Management tool, Oki developed the LSF system to support both users who can access
Oki Semiconductor
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