ADCMP605BCPZ-WP(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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ADCMP605BCPZ-WP
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
ADCMP605BCPZ-WP Datasheet PDF : 16 Pages
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ADCMP604/ADCMP605
OUTLINE DIMENSIONS
2.20
2.00
1.80
1.35
6
5
4
2.40
1.25
2.10
1.15
1
2
3
1.80
PIN 1
1.30 BSC
1.00
0.90
0.70
0.65 BSC
1.10
0.40
0.80
0.10
0.46
0.10 MAX
0.30
0.22
0.15
SEATING
PLANE
0.08
0.36
0.26
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203-AB
Figure 27. 6-Lead Thin Shrink Small Outline Transistor Package (SC70)
(KS-6)
Dimensions shown in millimeters
3.00
BSC SQ
0.75
0.55
0.60 MAX
0.35
PIN 1
INDICATOR
TOP
VIEW
0.45
2.75
BSC SQ
10
9
11
12
1
8
2
EXPOSED PAD
(BOTTOM VIEW)
7
3
654
12° MAX
1.00
0.85
0.80
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.50
BSC
SEATING
PLANE
0.30
0.23
0.20 REF
COPLANARITY
0.08
0.18
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1
EXCEPT FOR EXPOSED PAD DIMENSION.
PIN 1
INDICATOR
*1.45
1.30 SQ
1.15
0.25 MIN
Figure 28. 12-Lead Lead Frame Chip Scale Package (LFCSP-VQ)
3 mm × 3 mm Body, Very Thin Quad
(CP-12-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADCMP604BKSZ-R21
ADCMP604BKSZ-REEL71
ADCMP604BKSZ-RL1
ADCMP605BCPZ-WP1
ADCMP605BCPZ-R21
ADCMP605BCPZ-R71
EVAL-ADCMP605BCPZ1
1 Z = Pb-free part.
Temperature
Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
12-Lead Lead Frame Chip Scale Package (LFCSP-VQ)
12-Lead Lead Frame Chip Scale Package (LFCSP-VQ)
12-Lead Lead Frame Chip Scale Package (LFCSP-VQ)
Evaluation Board
Package
Option
KS-6
KS-6
KS-6
CP-12-1
CP-12-1
CP-12-1
Branding
G0Q
G0Q
G0Q
G0K
G0K
G0K
Rev. 0 | Page 14 of 16
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