ADCMP604BKSZ-R2 데이터 시트보기 (PDF) - Analog Devices
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ADCMP604BKSZ-R2
Analog Devices
ADCMP604BKSZ-R2 Datasheet PDF : 14 Pages
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ADCMP604/ADCMP605
Data Sheet
OUTLINE DIMENSIONS
2.20
2.00
1.80
1.35
6
5
4
2.40
1.25
2.10
1.15
1
2
3
1.80
PIN 1
1.30 BSC
1.00
0.90
0.70
0.65 BSC
1.10
0.40
0.80
0.10
0.46
0.10 MAX
0.30
0.22
0.15
SEATING
PLANE
0.08
0.36
0.26
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203-AB
Figure 27. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
PIN 1
INDICATOR
0.80
0.75
0.70
SEATING
PLANE
3.10
3.00 SQ
2.90
TOP VIEW
0.50
BSC
0.30
0.23
0.18
10
12
9
1
EXPOSED
PAD
7
3
PIN 1
INDICATOR
1.45
1.30 SQ
1.15
0.70
6
4
0.25 MIN
0.60
BOTTOM VIEW
0.50
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
ORDERING GUIDE
COMPLIANT TO JEDEC STANDARDS MO-220-WEED.
Figure 28. 12-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-12-4)
Dimensions shown in millimeters
Model1
ADCMP604BKSZ-R2
ADCMP604BKSZ-REEL7
ADCMP604BKSZ-RL
EVAL-ADCMP604BKSZ
ADCMP605BCPZ-WP
ADCMP605BCPZ-R2
ADCMP605BCPZ-R7
EVAL-ADCMP605BCPZ
1 Z = RoHS Compliant Part
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
6-Lead Thin Shrink Small Outline Transistor Package [SC70]
6-Lead Thin Shrink Small Outline Transistor Package [SC70]
6-Lead Thin Shrink Small Outline Transistor Package [SC70]
Evaluation Board
12-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
12-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
12-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
Package
Option
KS-6
KS-6
KS-6
Branding
G0Q
G0Q
G0Q
CP-12-4 G0K
CP-12-4 G0K
CP-12-4 G0K
©2006–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05916-0-1/15(C)
Rev. C | Page 14 of 14
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