ADCMP607(Rev0) 데이터 시트보기 (PDF) - Analog Devices

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ADCMP607
(Rev.:Rev0)

Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators

Analog Devices 

ADCMP606/ADCMP607

OUTLINE DIMENSIONS

2.20

2.00

1.80

1.35

6

5

4

2.40

1.25

2.10

1.15

1

2

3

1.80

PIN 1

1.30 BSC

1.00

0.90

0.70

0.65 BSC

1.10

0.40

0.80

0.10

0.46

0.10 MAX

0.30

0.22

0.15

SEATING

PLANE

0.08

0.36

0.26

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-203-AB

Figure 26. 6-Lead Thin Shrink Small Outline Transistor Package (SC70)

(KS-6)

Dimensions shown in millimeters

3.00

BSC SQ

0.75

0.55

0.60 MAX

0.35

PIN 1

INDICATOR

TOP

VIEW

0.45

2.75

BSC SQ

10

9

11

12

1

8

2

EXPOSED PAD

(BOTTOM VIEW)

7

3

654

12° MAX

1.00

0.85

0.80

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.50

BSC

SEATING

PLANE

0.30

0.23

0.20 REF

COPLANARITY

0.08

0.18

PIN 1

INDICATOR

*1.45

1.30 SQ

1.15

0.25 MIN

*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1

EXCEPT FOR EXPOSED PAD DIMENSION.

Figure 27. 12-Lead Lead Frame Chip Scale Package (LFCSP-VQ)

3 mm × 3 mm Body, Very Thin Quad

(CP-12-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model

ADCMP606BKSZ-R21

ADCMP606BKSZ-RL1

ADCMP606BKSZ-REEL71

ADCMP607BCPZ-R21

ADCMP607BCPZ-R71

ADCMP607BCPZ-WP1

1 Z = Pb-free part.

Temperature Range

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

Package Description

6-Lead Thin Shrink Small Outline Transistor Package (SC70)

6-Lead Thin Shrink Small Outline Transistor Package (SC70)

6-Lead Thin Shrink Small Outline Transistor Package (SC70)

12-Lead Lead Frame Chip Scale Package (LFCSP-VQ)

12-Lead Lead Frame Chip Scale Package (LFCSP-VQ)

12-Lead Lead Frame Chip Scale Package (LFCSP-VQ)

Package

Option

KS-6

KS-6

KS-6

CP-12-1

CP-12-1

CP-12-1

Branding

G0S

G0S

G0S

G0H

G0H

G0H

Rev. 0 | Page 14 of 16

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