ADCMP607BCPZ-WP 데이터 시트보기 (PDF) - Analog Devices
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ADCMP607BCPZ-WP Datasheet PDF : 14 Pages
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ADCMP606/ADCMP607
Data Sheet
OUTLINE DIMENSIONS
2.20
2.00
1.80
1.35
6
5
4
2.40
1.25
2.10
1.15
1
2
3
1.80
1.30 BSC
1.00
0.90
0.70
0.65 BSC
1.10
0.40
0.80
0.10
0.10 MAX
0.30
SEATING
0.22
PLANE
0.08
0.46
0.36
COPLANARITY
0.15
0.26
0.10
COMPLIANT TO JEDEC STANDARDS MO-203-AB
Figure 26. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
PIN 1
INDICATOR
0.80
0.75
0.70
SEATING
PLANE
3.10
3.00 SQ
2.90
TOP VIEW
0.50
BSC
0.30
0.23
0.18
10
12
9
1
EXPOSED
PAD
7
3
PIN 1
INDICATOR
1.65
1.50 SQ
1.35
0.50
6
4
0.25 MIN
0.40
BOTTOM VIEW
0.30
0.05 MAX
0.02 NOM
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.20 REF
ORDERING GUIDE
Model1
ADCMP606BKSZ-R2
ADCMP606BKSZ-REEL7
EVAL-ADCMP606BKSZ
ADCMP607BCPZ-R2
ADCMP607BCPZ-R7
ADCMP607BCPZ-WP
EVAL-ADCMP607BCPZ
1 Z = RoHS Compliant Part.
COMPLIANT TO JEDEC STANDARDS MO-220-WEED.
Figure 27. 12-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm and 0.75 mm Package Height
(CP-12-5)
Dimensions shown in millimeters
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
6-Lead Thin Shrink Small Outline Transistor Package [SC70]
6-Lead Thin Shrink Small Outline Transistor Package [SC70]
Evaluation Board
12-Lead Lead Frame Chip Scale Package [LFCSP]
12-Lead Lead Frame Chip Scale Package [LFCSP]
12-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Package
Option
KS-6
KS-6
CP-12-5
CP-12-5
CP-12-5
Branding
G0S
G0S
G0H
G0H
G0H
©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05917-0-4/16(C)
Rev. C | Page 14 of 14
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