NT68625 데이터 시트보기 (PDF) - Unspecified

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NT68625

Flat Panel Monitor Controller

Unspecified 

NT68665/NT68625

34 PB7*

DDC_SDA1*

35 PB6*

DDC_SCL1*

36 PA3

PWM5

37 PA4*

PWM6*

38 PA5*

PWM7*

39 PA6*

PWM8*

40 PA7*

PWM9*

41 HSYNCI1

42 VSYNCI0/TOUTP

43 PLL_ GND

44 TCLK

45 PLL_ VDD

46 PB5*

DDC_SDA0*/

HDCP_SDA

47 PB4*

DDC_SCL0*/

HDCP_SCL

48

RSTn /PD5

49 SDA/P35

T1

50 SCL

P34

T0

51 IRQn

52 CVDD

I/O

I/O

I/O

I/O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I

O

Power

I

Power

I/O

I/O

I/O

I/O

I/O

I/O

I

O

I/O

I

O

Power

I/O Pin; Open-Drain with Schmitt Trigger Input

5V Open-Drain Serial Data I/O Pin for the DDC Port 1 and

the slave/master I2C-Bus Port 1

5V I/O Pin; Open-Drain with Schmitt Trigger Input

5V Open-Drain Serial Clock I/O Pin for the DDC Port 1

and the slave/master I2C-Bus Port 1

I/O Pin; Schmitt Trigger Input

PWM-Type D/A Converter; 3.3V Push-Pull Structure

I/O Pin; Open-Drain Structure with Schmitt Trigger Input

PWM-Type D/A Converter; 5V Open-Drain Structure

I/O Pin; Open-Drain Structure with Schmitt Trigger Input

PWM-Type D/A Converter; 5V Open-Drain Structure

I/O Pin; Open-Drain Structure with Schmitt Trigger Input

PWM-Type D/A Converter; 5V Open-Drain Structure

I/O Pin; Open-Drain Structure with Schmitt Trigger Input

PWM-Type D/A Converter; 5V Open-Drain Structure

VGA Port Channel 1 Horizontal Sync Input with Schmitt

trigger. (Schmitt triggered, 5V tolerant)

VGA Port Channel 1 Vertical Sync Input with Schmitt

trigger / Testing pin for ADC

(Schmitt triggered, 5V tolerant)

Core Logic Ground pin for PLL.

Reference clock Input

Core logic power supply (1.8V) pin for PLL. External

capacitor (0.1uF) connected is recommended.

5V I/O Pin; Open-Drain with Schmitt Trigger Input

5V Open-Drain Serial Data I/O Pin for the DDC Port 0 and

the slave/master I2C-Bus Port 0/

For DVI HDCP communication interface Serial Data In/Out

(5V tolerant)

5V I/O Pin; Open-Drain with Schmitt Trigger Input

5V Open-Drain Serial Clock I/O Pin for the DDC Port 0

and the slave/master I2C-Bus Port 0/

For DVI HDCP communication interface Serial Clock

(5V tolerant)

System Reset;

I/O Pin; Push-Pull Structure with Schmitt Trigger Input

(5V tolerant)

Host Interface Serial Data In/Out. Incorporate Schmitt

trigger buffer & spike filter/ GPIO Port-35 of Micro-

Processor F8031 (5V tolerant)

Counter/Timer T1 Input of Micro-Processor F8031

Host Interface Serial Clock. Incorporate Schmitt trigger

buffer & spike filter (5V tolerant)

GPIO Port-34 of Micro-Processor F8031

Counter/Timer T0 Input of Micro-Processor F8031

Interrupt Request

Core logic power supply (1.8V) pin. External capacitor

(0.1uF) connected is recommended.

2006-02-09

12

Ver. 0.40

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