MAX6756UKLD0 데이터 시트보기 (PDF) - Maxim Integrated

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MAX6756UKLD0

Low-Power, Single/Dual-Voltage Window Detectors

Maxim Integrated 

MAX6754–MAX6764

Low-Power, Single/Dual-Voltage Window Detectors

V+

R1

UVIN MAX6763/MAX6764

UV

UVTH

R2

VCC

INTERNAL

REFERENCE

0.5V

OVTH

UV MONITOR

GND

OV

OVIN

R3

OV MONITOR

V+ x R3

OVERVOLTAGE ASSERTS WHEN

> 0.5V

R1 + R2 + R3

V+ x (R2 + R3)

UNDERVOLTAGE ASSERTS WHEN

< 0.5V

R1 + R2 + R3

Figure 6. Setting the Undervoltage/Overvoltage Window

Choose R2 to have a resistance of up to 500kΩ.

Calculate R1 by:

R1 = ((V+ - 0.4255V) x R2) / 0.4255V

The MAX6763/MAX6764 provide inputs to a window

detector allowing the programming of the threshold

voltage to within VCC (see Figure 6).

Choose R1, R2, and R3 such that:

(V+ / (R1 + R2 + R3)) ≥ 1μA

SET

The MAX6754–MAX6762 allow the setting of the window

voltage range of the voltage detector. Connect SET to

GND to set a ±5% window. Connect SET to VCC for a

±10% window. Bias SET to VCC / 2 for a ±15% window.

Manual Reset (MR)

The MAX6754–MAX6762 include an active-low manual

reset input. Drive MR low to assert a reset output

(MAX6754/MAX6755/MAX6756) or an undervoltage output

(MAX6757/MAX6758/MAX6759). The output remains

asserted for the specified propagation delay time (see

Figure 7a and Figure 7b) after MR goes high. MR is inter-

nally pulled to VCC with a 26kΩ resistor.

Overvoltage Latch Control Input (OVLATCH)

The MAX6760/MAX6761/MAX6762 provide an overvoltage

latch control input (OVLATCH). Drive OVLATCH high

to latch the overvoltage output for any VCC or VCC2

overvoltage condition. Drive OVLATCH low to clear the

latch after overvoltage conditions have been removed.

The latch is transparent when OVLATCH is connected to

GND. OVLATCH is a high impedance input. Use external

pullup or pulldown.

Reset, Undervoltage, and Overvoltage

Outputs (RESET, RESET, UV, UV, OV)

RESET, RESET, UV, UV, and OV outputs assert when

the monitored supply is below the selected UVTH threshold

or above the selected OVTH threshold. The reset output

deasserts after the specified timeout period when the

monitored supply rises above the UVTH threshold or

drops below the OVTH threshold. The push-pull versions

are referenced to VCC.

The MAX6760/MAX6761/MAX6762 monitor both VCC

and VCC2. An undervoltage/overvoltage condition on

either voltage supply asserts the corresponding output.

RESET and UV are guaranteed to be in the correct logic

state when VCC or VCC2 > 1V.

MR

RESET, UV

tD-MR

tMR_P

Figure 7a. Manual RESET/RESET Timing Diagram

VCC

tD-UV

RESET, UV

tRP

(RESET IS THE COMPLEMENT OF RESET)

Figure 7b. VCC/RESET, UV Timing Diagram

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