R5F71323AD80FPV 데이터 시트보기 (PDF) - Renesas Electronics

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R5F71323AD80FPV

Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Renesas Electronics 

14.4 Operation ........................................................................................................................... 563

14.4.1 Overview .............................................................................................................. 563

14.4.2 Operation in Asynchronous Mode ........................................................................ 565

14.4.3 Clock Synchronous Mode..................................................................................... 575

14.4.4 Multiprocessor Communication Function ............................................................ 584

14.4.5 Multiprocessor Serial Data Transmission ............................................................. 586

14.4.6 Multiprocessor Serial Data Reception .................................................................. 587

14.5 SCI Interrupt Sources and DTC ......................................................................................... 590

14.6 Serial Port Register (SCSPTR) and SCI Pins .................................................................... 591

14.7 Usage Notes ....................................................................................................................... 593

14.7.1 SCTDR Writing and TDRE Flag.......................................................................... 593

14.7.2 Multiple Receive Error Occurrence ...................................................................... 593

14.7.3 Break Detection and Processing ........................................................................... 594

14.7.4 Sending a Break Signal......................................................................................... 594

14.7.5 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) ...... 594

14.7.6 Note on Using DTC .............................................................................................. 596

14.7.7 Note on Using External Clock in Clock Synchronous Mode................................ 596

14.7.8 Module Standby Mode Setting ............................................................................. 596

Section 15 Synchronous Serial Communication Unit (SSU) ............................ 597

15.1 Features.............................................................................................................................. 597

15.2 Input/Output Pins............................................................................................................... 599

15.3 Register Descriptions ......................................................................................................... 600

15.3.1 SS Control Register H (SSCRH) .......................................................................... 601

15.3.2 SS Control Register L (SSCRL) ........................................................................... 603

15.3.3 SS Mode Register (SSMR) ................................................................................... 604

15.3.4 SS Enable Register (SSER) .................................................................................. 606

15.3.5 SS Status Register (SSSR) .................................................................................... 607

15.3.6 SS Control Register 2 (SSCR2) ............................................................................ 610

15.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................... 611

15.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3).................................... 612

15.3.9 SS Shift Register (SSTRSR)................................................................................. 613

15.4 Operation ........................................................................................................................... 614

15.4.1 Transfer Clock ...................................................................................................... 614

15.4.2 Relationship of Clock Phase, Polarity, and Data .................................................. 614

15.4.3 Relationship between Data Input/Output Pins and Shift Register ........................ 615

15.4.4 Communication Modes and Pin Functions ........................................................... 617

15.4.5 SSU Mode............................................................................................................. 619

15.4.6 SCS Pin Control and Conflict Error...................................................................... 628

15.4.7 Clock Synchronous Communication Mode .......................................................... 630

Rev. 3.00 Jan. 18, 2010 Page xvi of xxiv

REJ09B0402-0300

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