R5F7132 데이터 시트보기 (PDF) - Renesas Electronics
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R5F7132 Datasheet PDF : 1184 Pages
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15.5 SSU Interrupt Sources and DTC ........................................................................................ 636
15.6 Usage Notes ....................................................................................................................... 637
15.6.1 Module Standby Mode Setting ............................................................................. 637
15.6.2 Access to SSTDR and SSRDR Registers.............................................................. 637
15.6.3 Continuous Transmission/Reception in SSU Slave Mode.................................... 637
15.6.4 Note for Reception Operations in SSU Slave Mode ............................................. 637
15.6.5 Note on Master Transmission and Master Reception Operations in SSU Mode .. 638
15.6.6 Note on DTC Transfers......................................................................................... 638
Section 16 I2C Bus Interface 2 (I2C2) ................................................................639
16.1 Features.............................................................................................................................. 639
16.2 Input/Output Pins ............................................................................................................... 642
16.3 Register Descriptions ......................................................................................................... 643
16.3.1 I2C Bus Control Register 1 (ICCR1) ..................................................................... 643
16.3.2 I2C Bus Control Register 2 (ICCR2) ..................................................................... 646
16.3.3 I2C Bus Mode Register (ICMR)............................................................................ 648
16.3.4 I2C Bus Interrupt Enable Register (ICIER) ........................................................... 650
16.3.5 I2C Bus Status Register (ICSR)............................................................................. 652
16.3.6 I2C Bus Slave Address Register (SAR)................................................................. 655
16.3.7 I2C Bus Transmit Data Register (ICDRT)............................................................. 656
16.3.8 I2C Bus Receive Data Register (ICDRR) .............................................................. 656
16.3.9 I2C Bus Shift Register (ICDRS)............................................................................ 656
16.3.10 NF2CYC Register (NF2CYC) .............................................................................. 657
16.4 Operation ........................................................................................................................... 658
16.4.1 I2C Bus Format...................................................................................................... 658
16.4.2 Master Transmit Operation ................................................................................... 659
16.4.3 Master Receive Operation..................................................................................... 661
16.4.4 Slave Transmit Operation ..................................................................................... 664
16.4.5 Slave Receive Operation....................................................................................... 667
16.4.6 Clock Synchronous Serial Format ........................................................................ 668
16.4.7 Noise Filter ........................................................................................................... 672
16.4.8 Example of Use..................................................................................................... 673
16.5 I2C2 Interrupt Sources........................................................................................................ 677
16.6 Operation Using the DTC .................................................................................................. 678
16.7 Bit Synchronous Circuit..................................................................................................... 679
16.8 Usage Note......................................................................................................................... 681
16.8.1 Module Standby Mode Setting ............................................................................. 681
16.8.2 Issuance of Stop Condition and Repeated Start Condition ................................... 681
16.8.3 Issuance of a Start Condition and Stop Condition in Sequence ............................ 681
16.8.4 Settings for Multi-Master Operation..................................................................... 682
Rev. 3.00 Jan. 18, 2010 Page xvii of xxiv
REJ09B0402-0300
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