AD8042(2004) 데이터 시트보기 (PDF) - Analog Devices

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AD8042
(Rev.:2004)

Dual 160 MHz Rail-to-Rail Amplifier

Analog Devices 

AD8042

HDSL Line Driver

HDSL or high-bit-rate digital subscriber line is becoming popu-

lar as a means to provide data communication at DS1 rates

(1.544 MBPS) over moderate distances via conventional tele-

phone twisted pair wires. In these systems, the transceiver at the

customer’s end is sometimes powered via the twisted pair from

a power source at the central office. It is sometimes required to

raise the dc voltage of the power source to compensate for IR

drops in long lines or lines with narrow gauge wires.

Because of this, it is highly desirable to keep the power consump-

tion of the customer’s transceiver as low as possible. One means

to realize significant power savings is to run the transceiver from

a ± 5 V supply instead of the more conventional ± 12 V.

The high output swing and current drive capability of the

AD8042 make it ideally suited to this application. Figure 12

shows a circuit for the analog portion of an HDSL transceiver

using the AD8042 as the line driver.

232⍀

VIN

0.001␮F

2k⍀

3k⍀

6

5

2k⍀

7

1/2

AD8042

3k⍀

2

1

3

1/2

AD8042

912⍀

0.0027␮F

2k⍀

0.001␮F

ATT

2718AF

93DJ39

1

4

VOUT

10

5

2

7

9

6

34⍀ 2k⍀

2k⍀

2

2k⍀

3

1 249⍀

VREC

1/4

2k⍀ AD8044

Figure 12. HDSL Line Driver

LAYOUT CONSIDERATIONS

The specified high speed performance of the AD8042 requires

careful attention to board layout and component selection.

Proper RF design techniques and low-pass parasitic component

selection are necessary.

The PCB should have a ground plane covering all unused

portions of the component side of the board to provide a low

impedance path. The ground plane should be removed from the

area near the input pins to reduce the stray capacitance.

Chip capacitors should be used for the supply bypassing. One

end should be connected to the ground plane and the other

within 1/8 inch of each power pin. An additional large

(0.47 mF–10 mF) tantalum electrolytic capacitor should be

connected in parallel, but not necessarily so close, to supply

current for fast, large signal changes at the output.

The feedback resistor should be located close to the inverting

input pin in order to keep the stray capacitance at this node to a

minimum. Capacitance variations of less than 1 pF at the

inverting input will significantly affect high speed performance.

Stripline design techniques should be used for long signal traces

(greater than about one inch). These should be designed with a

characteristic impedance of 50 W or 75 W and be properly termi-

nated at each end.

–14–

REV. C

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