SEG0 - SEG127
These pins provide the LCD column driving signal. Their voltage level is VSS during sleep mode and
standby mode.
S5150
For SSD1851, this pin must be connected to VSS.
For SSD1850, this pin must be connected to VDD.
CL
This pin is the external clock input for the device if external clock mode is selected by software command.
Under POR operation, this pin should be left opened and internal oscillator will be used after power on
reset.
N/C
These No Connection pins should NOT be connected to any signal pins nor shorted together. They
should be left open.
SSD1850/51 Series Rev 1.2
01/2003
13
SOLOMON